Arbitration Signals - IBM PowerPC 604 User Manual

address bus. The address signals and the transfer attribute signals control the
address transfer. The address parity and address parity error signals ensure the
integrity of the address transfer.
- Termination: After the address transfer, the system signals that the address tenure
is complete or that it must be repeated
• Data tenure
- Arbitration: To begin the data tenure, the 604 arbitrates for mastership of the data
bus.
- Transfer: After the 604 is the data bus master, it samples the data bus for read
operations or drives the data bus for write operations. The data parity and data
parity error signals ensure the integrity of the data transfer.
- Termination: Data termination signals are required after each data beat in a data
transfer. Note that in a single-beat transaction, the data termination signals also
indicate the end of the tenure, while in burst accesses, the data termination
signals apply to individual beats and indicate the end of the tenure only after the
final data beat.
The 604 generates an address-only bus transfer during the execution of dcbz, sync, eieio,
tlbie, tlbsync, and lwarx instructions, which use only the address bus with no data transfer
involved Additionally, the 604's retry capability provides an efficient snooping protocol
for systems with multiple memory systems (including caches) that must remain coherenL
8.2.1 Arbitration Signals
Arbitration for both address and data bus mastership is performed by a central, external
arbiter and, minimally, by the arbitration signals shown in Section 8.3.1, "Address Bus
Arbitration." Most arbiter implementations require additional signals to coordinate bus
master/slave/snooping activities. Note that address bus busy (ABB) and data bus busy
(DBB) are bidirectional signals. These signals are inputs unless the 604 has mastership of
one or both of the respective buses; they must be connected high through pull-up resistors
so that they remain negated when no devices have control of the buses.
The following list describes the address arbitration signals:
• BR
(bus request)-Assertion indicates that the 604 is requesting mastership of the
address bus.
• lJ'G
(bus grant)-Assertion indicates that the 604 may, with the proper
qualification, assume mastership of the address bus. A qualified bus grant occurs
when BG is asserted, ABB is negated, and ARTRY is negated during the current and
previous bus cycle.
If the 604 is parked, BR need not be asserted for the qualified bus grant.
• Alm
(address bus busy)-Assertion by the 604 indicates that the 604 is the
address bus master.
Chapter 8. System Interface Operation
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