IBM PowerPC 604 User Manual page 436

reserved instructions, 2-23
rfi,
4-11
segment register manipulation, A-27
string/multiple, serialization, 6-35
stwcx., 4-11
supervisor-level, A-39
support for lwan/stwcx., 8-52
sync, 4-11
system linkage, 2-46, A-26
lLB management instructions, A-27
tlbie, 2-56
tlbsync, 2-56
trap instructions, 2-45, A-26
INT
signal, 7-25, 8-50
Integer arithmetic instructions, 2-26, A-18
Integer compare instructions, 2-28, A-19
Integer load instructions, 2-35, A-22
Integer logical instructions, 2-28, A-19
Integer rotate and shift instructions, 2-29, A-20
Integer store instructions, 2-36, A-23
Integer unit
instruction timings, 6-35
overview, 1-10
Interrupt, external, 4-16
isync, 2-49, 4-11
ITLB organization, 5-24
K
Kill block operation, 3-20
L
U_INT signal, 7-28
Latency
definition, 6-2
execution latency, 6-7
minimizing latency, 8-24
Link
register (LR), 2-5
Load operations
1/0
load accesses, 8-41
Load/store
address generation, 2-35
byte reverse instructions, 2-37, A-23
floating-point load instructions, A-24
floating-point move instructions, 2-33, A-25
floating-point store instructions, 2-41, A-24
handling misalignment, 2-33
integer load instructions, 2-35, A-22
integer store instructions, 2-36, A-23
load/store multiple instructions, 2-38, A-23
memory synchronization instructions, A-24
string instructions, 2-39, A-24
Index
INDEX
Load/store wiit
execution timing, 6-39
overview, 1-11
Logical addresses
translation into physical addresses, 5-1
lwarx/stwcx.
M
general infonnation, 3-19
support, 8-52
Machine check exception, 4-13
MCP signal, 7-25
Memory accesses, 8-4, 8-6
Memory coherency
memory coherency actions, 3-8
memory/cache access attributes, 3-10
sequential consistency, 3-9
Memory coherency (M attribute), 3-10
Memory control instructions, 2-50, 2-54
Memory management unit
604-specific features, 5-2
address translation flow, 5-12
address translation mechanisms, 5-9, 5-12
block address translation, 5-9, 5-12, 5-20
block diagram,
5-6, 5-1,
5-8
exceptions, 5-16
features summary, 5-3
instructions and registers, 5-18
memory protection, 5-11
overview, 1-12
page address translation, 5-9, 5-12, 5-27
page history status, 5-12, 5-21-5-24
real addressing mode, 5-10, 5-12, 5-20
segment model, 5-20
Memory operations, features, 6-15
Memory synchronization
instructions, 2-47, A-24
Memory unit
queuing structure, 3-19
Memory/cache access modes,
see also WIMG
bits
perfonnance impact of write-back mode, 6-15
MESI protocol
enforcing memory coherency, 8-29
MESI state definitions, 3-11
Misaligned data transfer, 8-16
MMCRO register, 2-8, 2-11, 9-1, 9-6
MSR (machine state register)
FEO/FEl bits, 4-9
IP bit, 4-12
PMbit,2-6
POW bit, 4-21
Rlbit,4-10
settings due to exception, 4-12
mtcrf, perfonnance, 2-46, 6-44
lndex-5
111111