Write-Back Stage - IBM PowerPC 604 User Manual

If the completion logic detects an instruction containing exception status or an instruction
that can cause subsequent instructions to be flushed at completion (such as mtspr[xer],
instructions that set the summary overflow (SO) bit, and other instructions listed below),
all following instructions are cancelled, their execution results in the rename buffers are
discarded, and fetching resumes at the correct stream of instructions. Other architectural
registers, such as CTR, LR, and CR, are updated during this stage. A complete list of the
affected instructions is as follows:
• mtspr (xer)
• mcrxr
• isync
• Instructions that set the summary overflow, SO, bit
• lswx
with 0 bytes to load
• Floating-point arithmetic, frsp, fctiw, and fctiwz instructions that cause an
exception with FPSCR[VE] = 1
• A floating-point instruction that causes a floating-point zero divide with
FPSCR(ZE
=
1)
6.2.1.1.6 Write-Back Stage
The write-back stage is used to write back any information from the rename buffers that
was not written back by the complete stage.
As
mentioned in Section 6.2.1.1.5, "Complete Stage," each of the rename buffers has two
read ports for write-back, corresponding to the two ports provided for write-back for the
GPRs, FPRs, and CR
As
many as two results are copied from the write-back buffers to a
register per clock cycle. To compensate for the extra write-back stage, the GPR rename
buffer has 12 entries, which reduces the chances for dispatch stalls for applications that
depend heavily on integer instructions.
6.3 Memory Performance Considerations
Due to the 604's instruction throughput of four instructions per clock cycle, lack of data
bandwidth can become a performance bottleneck. In order for the 604
to
approach its
potential performance levels, it must be able to read and write data quickly and efficiently.
If there are many processors in a system environment, one processor may experience long
memory latencies while another bus master (for example, a direct memory access
controller) is using the external bus.
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PowerPC 604 RISC Microprocessor User's Manual