IBM PowerPC 604 User Manual page 171

Table 4-2. Exceptions and Conditions-Overview (Continued)
Exception
Vector Offset
Causing Conditions
Type
(hex)
OSI 00300
A OSI exception occurs when a data memory access caMot be pelformed for
any of the reasons described in Section 4.5.3, "OSI Exception (Ox00300)." Such
accesses can be generated by load/store instructions, certain memory control
Instructions, and certain cache control instructions.
ISi 00400
An ISi exception occurs when an instruction fetch caMot be pelformed for a
variety of reasons descrl>ed in Section 4.5.4, "ISi Exception (Ox00400)."
External 00500
An external interrupt occurs when the external exception signal,
Tm',
is
interrupt
asserted. This signal is expected to
remain asserted until the exception handler
begins execution. Once the signal Is detected, the 604 stops dispatching
instructions and
waits
for all dispatched instructions to complete. Any exceptions
associated with dispatched instructions are taken before the interrupt is taken.
Alignment 00600
An
alignment exception may occur when the processor cannot pelform a
memory access for reasons described in Section 4.5.6, "Alignment Exception
(Ox00600)." Note that the PowerPC architecture defines a wider range of
conditions that may cause an alignment exception than required in the 604. In
these cases, the 604 provides logic to handle these conditions without requiring
the processor to invoke the afignment exception handler.
Program 00700 A program exception Is caused by one of the foUowing exception conditions,
which correspond to bit settings in SRR1 and arise during execution of an
instruction:
.
Floating-point enabled exception-A floating-point enabled exception
condition is generated when either MSR[FEO) or MSR(FE1) and
FPSCR[FEX] are set. The settings of FEO and FE1 are descrl>ed in
Table4-4.
FPSCR[FEX] is set by the execution ol a floating-point instruction that
causes an enabled exception or by the execution of a Move to FPSCR
Instruction that sets
both
an exception condition bit and its corresponding
enable bit in the FPSCR. These exceptions are described in Chapter 3 ol
The Programming Environments Manual.
.
Illegal Instruction-An Illegal instruction program exception is generated
when execution ol an Instruction is attempted with an illegal opcode or iUegal
combination ol opcode and extended opcode fields or when execution ol an
optional instruction
not
provided In the specific implementation is attempted
(these do not include those optional instructions that are treated as no-ops).
The PowerPC instruction
set
is described in Section 2.3, "Instruction
Set
Summary."
.
Privileged instruction-A privileged instruction
type
program exception is
generated when the execution of a privileged instruction is attempted and the
MSR register user privilege bit, MSR[PR), is set. This exception is also
generated tor mtspr or mfspr with an invalid SPA field
if
spr(0)=1 and
MSR[PRJ= 1.
.
Trap-A trap
type
program exception is generated when any of the
conditions specified in a trap instruction is met.
For more information, refer to Section 4.5.7, "Program Exception (Ox00700)."
Floating-point 00800 Defined by the PowerPC architecture, but not Implemented in the 604.
unavailable
Decrementer
00900 The decrementer intenupt exception is taken if the interrupt is enabled and the
exception Is pending. The exception is created when the
most
significant bit
changes from O to 1.
If It
is not enabled, the exception remains pending until it is
taken.
4-4
PowerPC 604 RISC Microprocessor User's Manual