IBM PowerPC 604 User Manual page 247

- In the FPU, fadd is in the complete and write-back stages, fsub is in the final
execute stage, fmadd is in the second stage, and fmsub is in the first. The fadds
instruction is in dispatch, causing the final floating-point instruction, fsubs, to
stall in dispatch.
7. The following occurs in cycle 7:
- Integer instructions 4 and
5
are allowed to complete and writeback because the
previous fsub instruction completes. However, the next pair of integer
instructions (8 and 9) must wait in the complete stage until fmadd and fmsub
can complete. The add and subf instructions are in the dispatch stage along with
the previous fsubs instruction.
- The fsub instruction completes, allowing integer instructions 4 and
5
to
complete. Floating-point instructions continue to move through the floating-
point pipeline with fmadd in the final execute stage, fmsub in the second stage,
and fadds in the first. The final floating-point instruction, fsubs, is allowed to
dispatch.
8. The following occurs in cycle 8:
- Integer instructions 8 and 9 continue to wait in the complete stage until fmsub
can complete. The add and subf instructions move into execute stage along with
the previous fsubs instruction, which is in the first stage of execute.
- The fmadd instruction completes and writes back and the subsequent floating-
point instructions each move to the next stage in the floating-point pipeline.
9. The following occurs in cycle 9:
- Integer instructions 8 and 9 are allowed to complete with the fmsub instruction.
However, the final pair of integer instructions (12and13) must wait in the
complete stage until fadds and fsubs can complete and write back.
- The fmsub instruction completes and writes back and the subsequent floating-
point instructions each move to the next stage in the floating-point pipeline.
10. The following occurs in cycle 10:
- The two remaining integer instructions remain in the complete stage until the
fsubs instruction completes.
- The fadds instruction completes and writes back and the remaining floating-
point instruction, fsubs, is in the last execute stage in the floating-point pipeline.
11. In cycle 11 all remaining instructions complete.
Note that the double-precision floating-point add instructions each has a latency of three
cycles (assuming no register dependencies) but can be fully pipelined and achieve a
throughput of one floating-point instruction per clock cycle.
Chapter 6. Instruction Timing
6·21