IBM PowerPC 604 User Manual page 429

F
Floating-point register (FPR). Any of the 32 registers in the floating-point
register file. These registers provide the source operands and
destination results for floating-point instructions. Load instructions
move data from memory
to
FPRs, and store instructions move data
from FPRs to memory.
Fraction. The field of the significand that lies to the right of its implied binary
point.
G
General-purpose register (GPR). Any of the 32 registers in the register file.
These registers provide the source operands and destination results
for all data manipulation instructions. Load instructions move data
from memory
to
registers, and store instructions move data from
registers to memory.
I
IEEE 754. A standard written by the Institute of Electrical and Electronics
Engineers that defines operations of binary floating-point arithmetic
and representations of binary floating-point numbers.
Interrupt. An asynchronous exception.
K
Kill. An operation that causes a cache block to be invalidated.
L
Latency. The number of clock cycles necessary to execute an instruction and
make ready the results of that instruction.
Little-endian. A byte-ordering method in memory where the address
n
of a
word corresponds to the least significant byte. In an addressed
memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3
being the most significant byte.
M
Mantissa. The decimal part of logarithm.
Memory-mapped accesses. Accesses whose addresses use the segmented or
block address translation mechanisms provided by the MMU and
that occur externally with the bus protocol defined for memory.
Memory coherency. Refers to memory agreement between caches in a
multiple processor and system memory (for example, MESI cache -
coherency).
Glossary of Terms and Abbreviations
Glossary-3