IBM PowerPC 604 User Manual page 318

The following list describes the data arbitration signals:
• mrG
(data bus grant)-Indicates that the 604 may, with the proper qualification,
assume mastership of the data bus. A qualified data bus grant occurs when DBG is
asserted while DBB, DRTRY, and ARTRY are negated (although ARTRY may
actually be asserted at the time DBG is asserted due to the snoop of a later address
tenure).
The DBB signal is driven by the current bus master, DRTRY is only driven from the
bus, and ARTRY is from the bus, but only for the address bus tenure associated with
the current data bus tenure (that is, not from another address tenure).
• DBWO
(data bus write only)-Assertion indicates that the 604 may perform the
data bus tenure for an outstanding write address even if a read address is pipelined
before the write address. If DBWO is asserted, the 604 will assume data bus
mastership for a pending data bus write operation; the 604 will take the data bus for
a pending read operation if this input is asserted along with DBG and no write is
pending. Care must be taken with DBWO to ensure the desired write is queued (for
example, a cache-line snoop push-out operation).
• Dim
(data bus busy)-Assertion by the 604 indicates that the 604 is the data bus
master. The 604 always assumes data bus mastership if it needs the data bus and is
given a qualified data bus grant (see DBG).
For more detailed information on the arbitration signals, refer to Section 8.3.1,
"Address Bus Arbitration," and Section 8.4.1, "Data Bus Arbitration."
Note that while operating in fast-L2/data streaming mode, DBB becomes a 604 output-only
signal and is driven in the same manner as before. If systems using the 604 in f ast-L2/data
streaming mode also implement data streaming across multiple masters, the DBB signal
must not be common among processors to avoid contention problems when one processor
is negating DBB while another is asserting DBB. Table 8-1 describes the bus arbitration
signals provided by the 604.
Table 8-1. PowerPC 604 Microprocessor Bus Arbitration Slgnals
SlgnalName Mnemonic Signal Type Signal Connection Requirements
Bus request
BR
Output One per processor
Bus grant
~
lll>UI
One per processor
Address bus busy
Ami
lll>ut/Outpul Common among processors
Data bus grant
~
lll>UI One per processor
Data bus busy
nBB
lll>ut/Output Common among processors
(One per processor if in fast-L2/data
streaming mode, and data streaming across
multiple processors is implemented.)
8-8
PowerPC 604 RISC Microprocessor User's Manual