Segment Register Manipulation Instructions (Oea); Translation Lookaside Buffer Management Lnstructions-(Oea) - IBM PowerPC 604 User Manual

2.3.6.3.2 Segment Register Manipulation Instructions (OEA)
The instructions listed in Table 2-45 provide access to the segment registers for 32-bit
implementations. These instructions operate completely independently of the MSR[IR] and
MSR[DR] bit settings. Refer to "Synchronization Requirements for Special Registers and
for Lookaside Buffers," in Chapter 2, "PowerPC Register Set," of
The Programming
Environments Manual
for serialization requirements and other recommended precautions
to observe when manipulating the segment registers.
Table 2-45. Segment Register Manipulation Instructions
Name Mnemonic Operand Syntax
Move to Segment Register mtsr SR,rS
Move to Segment Register Indirect
mtsrln
rS,rB
Move from Segment Register mfsr rD,SR
Move from Segment Register Indirect mfsrln rD,rB
2.3.6.3.3 Translation Lookaside Buffer Management lnstructions-(OEA)
The address translation mechanism is defined in terms of segment descriptors and page
table entries (PTEs) used by PowerPC processors to locate the logical to physical address
mapping for a particular access. These segment descriptors and PTEs reside in segment
tables and page tables in memory, respectively.
Refer to Chapter 7, "Memory Management" for more information about TLB operation.
Table 2-46 summarizes the operation of the TLB instructions in the 604.
Chapter 2. PowerPC 604 Processor Programming Model 2-55
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