Memory Management - IBM PowerPC 604 User Manual

Chapter 5
Memory Management
This chapter describes the PowerPC 604 microprocessor's implementation of the memory
management unit (MMU) specifications provided by the operating environment
architecture (OEA) for PowerPC processors. The primary function of the MMU in a
PowerPC processor is the translation of logical (effective) addresses to physical addresses
(referred to as real addresses in the architecture specification) for memory accesses, 1/0
accesses (most 1/0 accesses are assumed to be memory-mapped), and direct-store interface -
accesses. In addition, the MMU provides access protection on a segment, block or page
basis. This chapter describes the specific hardware used to implement the MMU model of
the OEA in the 604. Refer to Chapter 7, "Memory Management," in
The Programming
Environments Manual
for a complete description of the conceptual model.
Two general types of accesses generated by PowerPC processors require address
translation-instruction accesses and data accesses to memory generated by load and store
instructions. Generally, the address translation mechanism is defined in terms of segment
descriptors and page tables used by PowerPC processors to locate the effective-to-physical
address mapping for instruction and data accesses. The segment information translates the
effective address to an interim virtual address, and the page table information translates the
interim virtual address to a physical address.
The segment descriptors, used to generate the interim virtual addresses, are stored as
on-chip segment registers on 32-bit implementations (such as the 604). In addition, two
translation lookaside buffers (TLBs) are implemented on the 604 to keep recently-used
page address translations on-chip. Although the PowerPC OEA describes one MMU
(conceptually), the 604 hardware maintains separate TLBs and table search resources for
instruction and data accesses that can be performed independently (and simultaneously).
Therefore, the 604 is described as having two MMUs, one for instruction accesses (IMMU)
and one for data accesses (DMMU).
The block address translation (BAT) mechanism is a software-controlled array that stores
the available block address translations on-chip. BAT array entries are implemented as
pairs of BAT registers that are accessible as supervisor special-purpose registers (SPRs).
There are separate instruction and data BAT mechanisms, and in the 604, they reside in the
instruction and data MMUs respectively.
Chapter 5. Memory Management
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