IBM PowerPC 604 User Manual page 7

Paragraph
Number
1.3.1
1.3.2
1.3.2.1
1.3.2.2
1.3.2.3
1.3.2.4
1.3.2.5
1.3.2.6
1.3.2.7
1.3.2.7.1
1.3.2.7.2
1.3.3
1.3.3.1
1.3.3.1.1
1.3.3.1.2
1.3.4
1.3.5
1.4
1.5
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.2
2.1.2.3
2.1.2.4
2.1.2.4.1
2.1.2.4.2
2.1.2.4.3
2.1.2.4.4
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.3
2.3.1
2.3.1.1
iv
CONTENTS
Tltle
Page
Number
Levels of the PowerPC Architecture .............................................................. 1-19
Registers and Programming Model ................................................................ 1-20
General-Purpose Registers (GPRs) ............................................................ 1-22
Floating-Point Registers (FPRs) ................................................................ 1-22
Condition Register (CR) ••.•.•.•.............•..........•..............................••....••....• 1-22
Floating-Point Status and Control Register (FPSCR) ..................••.•.•....... 1-23
Machine State Register (MSR) ...........•••......••..............................•.•.••........ 1-23
Segment Registers (SRs) ••••.•..............•••........•..........................•..•.••...•...... 1-23
Special-Purpose Registers (SPRs) ••.•.....................................••..•............... 1-23
User-Level SPRs •••..•.....•......••.....•••...............................••••...•.•............... 1-23
Supervisor-Level SPRs ....•••••....••••.....................................••••••.............. 1-23
Instruction Set and Addressing Modes .......................................................... 1-25
PowerPC Instruction Set and Addressing Modles ....................•....••.••........ 1-25
Instruction Set ........................................................................................ 1-25
Calculating Effective Addresses ............................................................ 1-27
Exception Model .................•.•.••......................•......•...........•.....•.••••.••............. 1-28
Instruction Timing ......................................................................................... 1-33
Power Management-Nap Mode ...................................................................... 1-35
Performance Monitor •........••••.•...........................•............................••••••••.......... 1-35
Chapter 2
PowerPC 604 Processor Programming Model
The PowerPC 604 Processor Register Set ........................................................... 2-1
Register Set ...................................................................................................... 2-2
604-Specific Registers ..................................................................................... 2-8
Instruction Address Breakpoint Register (IABR) ....................•.•.............•.•. 2-8
Processor Identification Register (PIR) ....................................................... 2-9
Hardware Implementation-Dependent Register 0 .................••.................• 2-10
Performance Monitor Registers ......•••••.••..•••.............•.••••.••.............•...•..•... 2-11
Monitor Mode Control Register 0 (MMCRO) ....................................... 2-11
Performance Monitor Counter Registers (PMCl and PMC2) ..........•••.• 2-13
Sampled Instruction Address Register (SIA) ............•.•.••••..................•. 2-15
Sampled Data Address Register (SDA) ................................................. 2-16
Operand Conventions ......................................................................................... 2-16
Floating-Point Execution Models-UISA ............•••••••.....................•••.......... 2-16
Da~
Organization in Memory and Data Transfers ..•••••••••••.•.••............•••••..... 2-17
Alignment and Misaligned Accesses .......................•..••••••••.•................••••..... 2-17
Floating-Point Operand ...........••••.••.............................•.•••••••.••••..................... 2-17
Effect of Operand Placement on Performance •••..............•..••••••...........••••.•••. 2-19
Instruction Set Summary .................................................................................... 2-19
Classes of Instructions ................................................................................... 2-21
Definition of Boundedly Undefined .......................................................... 2-21
PowerPC 604 RISC Microprocessor User's Manual