Calculating Effective Addresses - IBM PowerPC 604 User Manual

• Memory/cache control instructions-These instructions provide control of caches,
TLBs, and segment registers.
- User- and supervisor-level cache instructions
- Segment register manipulation instructions
- Translation lookaside buffer management instructions
• Optional instructions-the 604 implements the following optional instructions:
- The eciwx/ecowx instruction pair
- The TLB Synchronize instruction (tlbsync)
- Optional graphics instructions:
- Store Floating-Point as Integer Word Indexed (stfiwx)
- Floating Reciprocal Estimate Single (fres)
- Floating Reciprocal Square Root Estimate (frsqrte)
- Floating Select (fsel)
Note that this grouping of the instructions does not indicate which execution unit executes
a particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point
instructions operate on single-precision (one word) and double-precision (one double
word) floating-point operands. The PowerPC architecture uses instructions that are four
bytes long and word-aligned. It provides for byte, half-word, and word operand loads and
stores between memory and a set of 32 GPRs. It also provides for word and double-word
operand loads and stores between memory and a set of 32 FPRs.
Computational instructions do not modify memory. To use a memory operand in a
computation and then modify the same or another memory location, the memory contents
must be loaded into a register, modified, and then written back to the target location with
specific store instructions.
PowerPC processors follow the program flow when they are in the normal execution state.
However, the flow of instructions can be interrupted directly by the execution of an
instruction or by an asynchronous event. Either kind of exception may cause one of several
components of the system software to be invoked.
1.3.3.1.2 Calculating Effective Addresses
The effective address (EA) is the 32-bit address computed by the processor when executing
a memory access or branch instruction or when fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
• EA= (r AIO) +offset (including offset= 0) (register indirect with immediate index)
• EA= (rAIO) + rB (register indirect with index)
These simple. addressing modes allow efficient address generation for memory accesses.
Calculation of the effective address for aligned transfers occurs in a single clock cycle.
Chapter 1. Overview
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