IBM PowerPC 604 User Manual page 143

Table 3-4. Response to Bus Transactions
Transaction
Response
Clean
block The clean operation is an address-only bus transaction, initiated by executing a dcbst
Instruction. This operation affects only blocks marked as modified (M). Assuming the
•signal is asserted, modified blocks are pushed out to memory, changing the state
toE.
Rush block
The flush operation is an address-only bus transaction Initiated by executing a dcbf
instruction. Assuming the
<me
signal is asserted, the flush block operation resutts in the
following:
• If the addressed block is in the S or E state, the state ol the addressed block is
changed to I.
• If the addressed block is in the M state, the snooping device
asserts~
and §JD,
the modified block is pushed out of the cache, and its state is changed to I.
Write-with-flush Write-with-flush and write-with-flush-atomic operations are issued by a processor after
Write-with-flush-atomic
executing stores or stwcx., respectively to memory in a variety ol different states,
particularly noncacheable and write-through. 60x processors do not use this transaction
code for burst transfers, but system use for bursts is not precluded. if they appear on the
bus and the GBL bit is asserted, the 60x processors have the same snoop response as
for flush block, except that a hit on the reservation address causes loss ol the
reservation.
KiUblock
Kill block is an address-only transaction issued by a processor after executing a dcbl
instruction, a dcbz instruction to a location marked I or S, or a write operation to a block
marked S. If a kill-block transaction appears on the bus, and the GBL bit is asserted, the
addressed block is forced to the I state if it is in the cache.
Write-with-kill
In a write-witlH<ill operation, the processor snoops the cache for a copy of the
addressed block. If one is found, an additional snoop action is initiated intemaUy and the
block is forced to the I state, killing modified data that may have been In the block. In
addition to snooping the cache, the three-entry write queue is also snooped. A kill
operation that hits an entry In the write queue purges that entry from the queue.
Read Read Is used by most single-beat or burst reads on the bus. A read on the bus with the
Read-atomic GBL
bit
asserted causes the following snoop responses:
• If the addressed block is in the cache in the I state, the processor takes no action.
• If the addressed block is in the cache In the S state, the processor asserts the §m
snoop
status signal.
• If the addressed block is in the cache in the E state, the processor asserts the
SFm
snoop status signal and changes the state of that cache block to S.
• If the addressed block is in the cache In the M state, the processor asserts both the
~and
mm
snoop status signals and changes the state ol that block in the
cache from E to S.
Read-atomic operations appear on the bus in response to IWarx Instruction and receive
the same snooping treatment as a read operation.
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PowerPC 604 RISC Microproceeaor User's Manual