IBM PowerPC 604 User Manual page 264

-
their CR results to the BPU for fast branch resolution without waiting for the instruction
to
be retired by the completion unit and the CR
to
be updated. Refer
to
Table 6-2 for floating-
point instruction execution timing.
As
shown in Figure 6-16, The FPU on the 604 is a single-pass, double-precision unit. This
means that both single- and double-precision floating-point operations require one-
pass/one-cycle throughput with a latency of three cycles. This hardware implementation
supports the IEEE 754-1985 standard for floating-point arithmetic, including support for
the NaNs and denormalized data types.
Instructions are obtained from the instruction dispatcher and placed in the reservation
station queue. The operand sources are the FPR, the floating-point rename buffers, and the
result buses. The result of an FPU operation is written
to
the floating-point rename buffers
and
to
the reservation stations. Instructions are executed from the reservation station queue
in the order they were originally dispatched.
Instruction
Di~ch
Bus
.L
FPR Operand Buses
,
L
,
FPU Result Bus
L
LS Result Bus
,
.L
,
FPSCR Bus
.L
,
Q
a
Q
a
_r
Queue 1
Jv]
-L
t
' '
j_
--
J
Queueo
lvJ
A'
l_
• Q
I
•
.9
Floating-Point Multiply
~
Stage 1
~
~
Add Pre-Alignment
·O
0 ~
Floating-Point Pipeline Add
Stage 2
~
Normalize/Round/Write-Back. Stages
J:'
Result Status Bus
..L
,
Figure 6-16. FPU Block Diagram
6-38
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