Event Selection - IBM PowerPC 604 User Manual

The following are states that can be monitored:
• (Supervisor) only
• (User) only
• (Marked and user) only
• (Not marked and user) only
• (Marked and supervisor) only
• (Not marked and supervisor) only
• (Marked) only
• (Not marked) only
In
addition, one of two unconditional counting modes may be specified:
• Counting is unconditionally enabled regardless of the states of MSR[PM] and
MSR[PR]. This can be accomplished by clearing MMCR0[0-4].
• Counting is unconditionally disabled regardless of the states of MSR[PM] and
MSR[PR]. This is done by setting MMCRO[O].
The performance monitor counters track how often a selected event occurs and are used
to
generate performance monitor exceptions when an overflow (most significant bit is a 1)
situation occurs. The 604 performance monitor contains two counters. This register is
cleared at startup and can
be
updated through an mtspr instruction.
The 32-bit registers can count up to Ox7FFFFFFF (2,147,483,648 in decimal) before
becoming negative. The most significant bit (bit 0) of both registers is used to determine if
an interrupt condition exists.
9.1.2.1 Event Selection
Event selection is handled through PMCl and PMC2, described in Table 9-2 and Table 9-3,
respectively. Event selection is described as follows:
• The event select fields are located in MMCRO. There are 7 bits associated with
PMCl and 6 bits associated with PMC2. Only the low order
5
bits are used for
selection. The higher order bits are reserved for future applications.
• In
the tables, a correlation is established between each counter, the events to be
traced, and the pattern required for the desired selection.
• The first five events are common to both counters. These are considered
to
be
reference events.
• Some events can have multiple occurrences per cycle, and therefore need two or
three bits to represent them. These events are number 2, 4, 14, 15 for PMCl and
2, 4, 8, 18 for PMC2.
Chapter 9. Performance Monitor 9-9