IBM PowerPC 604 User Manual page 12

Paragraph
Number
6.1
6.2
6.2.1
6.2.1.1
6.2.1.1.1
6.2.1.1.2
6.2.1.1.3
6.2.1.1.4
6.2.1.1.5
6.2.1.1.6
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.4.1
6.3.4.2
6.3.4.3
6.4
6.4.1
6.4.2
6.4.2.1
6.4.2.2
6.4.3
6.4.4
6.4.4.1
6.4.4.1.1
6.4.4.1.2
6.4.4.1.3
6.4.4.1.4
6.4.5
6.4.6
6.4.6.1
6.4.6.2
6.4.7
6.4.7.1
6.4.7.2
6.4.7.3
6.4.7.4
6.4.7.5
Contents
CONTENTS
Tltle
Chapter 6
Instruction Timing
Page
Number
Tenninology and Conventions .....••...........•.....•...............................................••.•. 6-1
Instruction Timing Overview .........................................................................••.•.. 6-3
Pipeline Structures ................•.......................................................................... 6-5
Description of Pipeline Stages .......•...................•......................................... 6-7
Fetch Stage .............................................................................................. 6-8
Decode Stage ........................................................................................... 6-9
Dispatch Stage ......................................................................................... 6-9
Execute Stage ........................................................................................ 6-10
Complete Stage ........................•...................................................•......... 6-11
Write-Back Stage ......•............................................................................ 6-12
Memory Perfonnance Considerations ............................................................... 6-12
MMU Overview ..................••.....•.........••........•..••.........•........••..............•••..•... 6-13
Cache Overview ....................................•...................................••................... 6-13
Bus Interface Overview ..........................................................................•...... 6-15
Memory Operations ....................................................................................... 6-15
Write-Back Mode •.........................................................................•.........•• 6-15
Write-Through Mode ....•..•..................••.••...........•..•..................•...............• 6-16
Cache-Inhibited Mode .........•..................................................................... 6-16
Timing Considerations ......................................................................................• 6-17
General Instruction Flow ............................................................................... 6-17
Instruction Fetch Timing ............................................................................... 6-18
Cache Hit Timing Exaillple ......................................................................• 6-18
Cache Miss Timing Example ............................................................•........ 6-22
Cache Arbitration .........................................................................•.............•... 6-24
Branch Prediction ...............................•...............•.................................••....... 6-24
Branch Timing Examples .......................................................................... 6-25
Timing Example-Branch Timing for a BT AC Hit .........••..••........•.....• 6-25
Timing Example-Branch with BT AC Miss/Decode Correction ...•..... 6-26
Timing Example-Branch with BT AC Miss/Dispatch Correction ....... 6-28
Timing Example-Branch with BT AC Miss/Execute Correction ........ 6-28
Speculative Execution .................................................................................... 6-29
Instruction Dispatch and Completion Considerations ................................... 6-30
Rename Register Operation ....................................................................... 6-31
Execution Unit Considerations .................................................................. 6-33
Instruction Serialization ................................................................................. 6-33
Dispatch Serialization Mode .••...........................................•.......•......••.....•• 6-34
Execution Serialization Mode ..................•..........•...................................... 6-34
Postdispatch Serialization Mode ................................................................ 6-34
Serialization of String/Multiple Instructions ............................................. 6-35
Serialization of Input/Output ..................................................................... 6-35
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