Segment Register Updates - IBM PowerPC 604 User Manual

The PowerPC OBA defines the tlbsync instruction that ensures that TLB invalidate
operations executed by this processor have caused all appropriate actions in other
processors. In a system that contains multiple processors, the dbsync functionality must
be
used in order to ensure proper synchronization with the other PowerPC processors. Note
that for compatibility with PowerPC 601 microprocessor systems a sync instruction must
also follow the tlbsync to ensure that the tlbsync has completed execution on this
processor.
Any processor, including the processor modifying the page table, may access the page table
at any time in an attempt to reload a TLB entry. An inconsistent page table entry must never
accidentally become visible; thus, there must be synchronization between modifications to
the valid bit and any other modifications (to avoid corrupted data). This requires as many
as two sync operations for each PI'E update.
Because the V, R, and C bits each reside in a distinct byte of a Pl'E, programs may update
these bits with byte store operations (without requiring any higher-level synchronization).
However, extreme care must be taken to ensure that no store overwrites one of these bytes
accidentally. Processors write referenced and changed bits with unsynchronized, atomic
byte store operations.
Explicitly altering certain MSR bits (using the mtmsr instruction), or explicitly altering
Pl'Es, or certain system registers, may have the side effect of changing the effective or
physical addresses from which the current instruction stream is
being
fetched. This kind of
side effect is defined as an implicit branch. Implicit branches are not supported and an
attempt to perform one causes boundedly undefined results. Therefore, PI'Es must not be
changed in a manner that causes an implicit branch. Chapter 2, "Power PC Register Set," in
The Programming Environments Manual,
lists the possible implicit branch conditions that
can occur when system registers and MSR bits are changed.
5.4. 7 Segment Register Updates
There are certain synchronization requirements for using the niove to segment register
instructions. These are described in "Synchronization Requirements for Special Registers
and for Lookaside Buffers" in Chapter 2, "PowerPC Register Set," in
The Programming
Environments Man-ual.
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PowerPC 604 RISC Mlcroprocesaor User's Manual