Performance Monitor - IBM PowerPC 604 User Manual

Chapter 9
Performance Monitor
The PowerPC 604 microprocessor provides a perfonnance monitor facility to monitor and
count predefined events such as processor clocks, misses in either the instruction cache or
the data cache, instructions dispatched to a particular execution unit, mispredicted
branches,
and
other occurrences. The count of such events (which may
be
an
approximation) can be used to trigger the perfonnance monitor exception. The
performance monitor facility is not defined by the ·PowerPC architecture.
The performance monitor can be used for the following:
• To increase system perfonnance with efficient software, especially in a
multiprocessing system. Memory hierarchy behavior must be monitored and studied
in order to develop algorithms that schedule tasks (and perhaps partition them) and
that structure and distribute data optimally.
• To improve processor architecture, the detailed behavior of the 604 's structure must
be known and understood in many software environments. Some environments may
not easily be characterized by a benchmark or trace.
• To help system developers bring up
and
debug their systems.
The perfonnance monitor uses the following 604-specific special-purpose registers (SPRs):
• Perfonnance monitor counters 1 and 2 (PMCl and PMC2)-two 32-bit counters
used to store the number of times a certain event has been detected
• The
monitor mode control register (MMCRO), which establishes the function of the
counters.
• Sampled instruction address and sampled data address registers (SIA and SDA).
Depending on how the performance monitor is configured, these registers point to
the data or instruction that caused a threshold-related performance monitor interrupt
The 604 supports a perfonnance monitor interrupt that is caused by a counter negative
condition or by a time-base flipped bit counter defined in the MMCRO register.
As
with other PowerPC interrupts, the performance monitor interrupt follows the normal
PowerPC exception model with a defined exception vector offset (OxOOFOO).
The
priority
of the performance monitor interrupt is below
the
external interrupt and above the
decrementer interrupt The contents of the SIA
and
SDA are
described
in Section 9.1.1.2.1,
Chapter 9. Performance Monitor
9-1