Memory Coherency-Mesi Protocol - IBM PowerPC 604 User Manual

Assertion of the TEA signal causes a machine check exception (and possibly a checkstop
condition within the 604). For more information, see Section 4.5.2, "Machine Check
Exception (Ox00200)." Note also that the 604 does not implement a synchronous error
capability for memory accesses. This means that the exception instruction pointer does not
point to the memory operation that caused the assertion of TEA, but to the instruction about
to be executed (perhaps several instructions later). However, assertion of TEA does not
invalidate data entering the GPR or the cache. Additionally, the corresponding address of
the access that caused TEA to be asserted is not latched by the 604. To recover, the
exception handler must determine and remedy the cause of the TEA, or the 604 must
be
reset; therefore, this function should only be used to flag fatal system conditions to the
processor (such as parity or uncorrectable ECC errors).
After the 604 has committed to run a transaction, that transaction must eventually complete.
Address retry causes the transaction to be restarted; TA wait states and DRTRY assertion
for reads delay termination of individual data beats. Eventually, however, the system must
either terminate the transaction or assert the TEA signal (and vector the 604 into a machine
check exception.) For this reason, care must be taken to check for the end of physical
memory and the location of certain system facilities to avoid memory accesses that result
in the generation of machine check exceptions.
Note that TEA generates a machine check exception depending on the ME bit in the MSR.
Clearing the machine check exception enable control bit leads to a true checkstop condition
(instruction execution halted and processor clock stopped); a machine check exception
occurs if the ME bit is set.
8.4.5 Memory Coherency-MESI Protocol
The 604 provides dedicated hardware to provide memory coherency by snooping bus
transactions. The address retry capability enforces the four-state, MESI cache-coherency
protocol (see Figure 8-15). In addition to the hardware required to monitor bus traffic for
coherency, the 604 has a cache port dedicated to snooping so that comparing cache entries
to address traffic on the bus does not tie up the 604's on-chip data cache.
The global (GBL) signal output, indicates whether the current transaction must
be
snooped
by other snooping devices on the bus. Address bus masters assert GBL to indicate that the
current transaction is a global access (that is, an access to memory shared by more than one
processor/cache). If GBL is not asserted for the transaction, that transaction is not snooped.
When other devices detect the GBL input asserted, they must respond by snooping the
broadcast address.
Normally, GBL reflects the M-bit value specified for the memory reference in the
corresponding translation descriptor(s). Note that care must be taken to minimize the
number of pages marked as global, because the retry protocol discussed in the previous
section is used to enforce coherency and can require significant bus bandwidth.
Chapter 8. System Interface Operation
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