Exception Definitions; Msr Setting Due To Exception - IBM PowerPC 604 User Manual

The operating system should set the MSR[RI] bit as described in Section 4.3.3, "Setting
MSR[RI]."
4.5 Exception Definitions
Table 4-5 shows all the types of exceptions that can occur with the 604 and the MSR bit
settings when the processor transitions to supervisor mode due to an exception. Depending
on the exception, certain of these bits are stored in SRRl when an exception is taken.
Table 4-5. MSR Setting Due to Exception
Exception
MSR Bit
Type
POW ILE EE PR
FP ME FEO
SE BE
FE1
IP IR
DR
RI LE
System reset
0
-
0 0 0
-
0 0 0 0
-
0 0 0
ILE
Machine 0
-
0 0 0 0 0
0 0
0
-
0
0
0
ILE
check
OSI
0
-
0 0 0
-
0 0 0 0
-
0 0 0 ILE
ISi
0
-
0 0 0
-
0 0 0 0
-
0 0 0 ILE
Extemal
0
-
0 0 0
-
0 0 0 0
-
0 0 0 ILE
Alignment 0
-
0
0
0
-
0 0
0
0
-
0 0 0
ILE
Program 0
-
0 0 0
-
0
0 0
0
-
0 0 0
ILE
Floating-
0
-
0 0 0
-
0 0 0 0
-
0 0 0
ILE
point
unavaDable
Decrementer
0
-
0 0 0
-
0 0
0
0
-
0 0
0
ILE
System call
0
-
0 0 0
-
0
0 0
0
-
0
0
0
ILE
Trace 0
-
0 0
0
-
0
0 0 0
-
0 0 0 ILE
exception
System
0
-
0 0 0 - 0
0 0
0
-
0 0 0
ILE
management
Performance
0
-
0 0 0
-
0 0 0 0
-
0 0 0
ILE
monitor
O
Bit is cleared.
ILE Bit is copied from the ILE bit in the MSR.
Bit is not altered
Reserved bits are read as if written as O.
The setting of the exception prefix bit (IP) determines how exceptions are vectored. If the
bit is cleared, exceptions are vectored to the physical address OxOOOn
nnnn
(where
nnnnn
is the vector offset); if IP is set, exceptions are vectored to the physical address
Ox.FFFn _
nnnn.
Table 4-2 shows the exception vector offset of the first instruction of the
exception handler routine for each exception type.
4-12
PowerPC 604 RISC Microprocessor User's Manual