IBM PowerPC 604 User Manual page 329

If an address retry is required, the ARTRY response will be asserted by a bus snooping
device as early as the second cycle after the assertion of TS. Once asserted, ARTRY must
remain asserted through the cycle after the assertion of AACK. The assertion of ARTRY
during the cycle after the assertion of AACK is referred to as a qualified ARTRY. An earlier
assertion of ARTRY during the address tenure is referred to as an early ARTRY.
As
a bus master, the 604 recognizes either an early or qualified ARTRY and prevents the
data tenure associated with the retried address tenure. If the data tenure has already begun,
the 604 aborts and terminates the data tenure immediately even if the burst data has been
received.
If the assertion of ARTRY is received up to or on the bus cycle following the first
(or only) assertion of TA for the data tenure, the 604 ignores the first data beat, and if it is
a load operation, does not forward data internally to the cache and execution units.
If the 604 is in fast-L2/data streaming mode, TA should not be asserted prior to the qualified
ARTRY cycle. If ARTRY is asserted after the first (or only) assertion of
TA,
improper
operation of the bus interface may result.
During
the
clock of a qualified ARTRY, the 604 also determines if it should negate BR and
ignore
BG
on the following cycle.
On
the following cycle, only the snooping master that
asserted ARTRY and needs to perform a snoop copy-back operation is allowed to assert
BR This guarantees the snooping master an opportunity
to
request
and
be granted the bus
before the just-retried master can restart its transaction.
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Figure 8-7. Snooped Address Cycle with ARTRY
Chapter 8. System Interface Operation
7 8
8-19