IBM PowerPC 604 User Manual page 371

to initiate a performance monitor interrupt, and specify the conditions under which
counting is enabled.
The MMCRO can be written
to
or read only in supervisor mode. The MMCRO includes
controls, such as counter enable control, counter overflow interrupt control, counter event
selection, and counter freeze control.
This register is cleared at power up. Reading this register does not change its contents. The
fields of the register are defined in Table 9-4.
Table 9-4. MMCRO Bit Settings
Bit Name Description
0 DIS Disable counting uncondltlonally
0 The values of the PMCn counters
can
be
changed by hardware.
1 The values of the PMCn counters
cannot
be changed by hardware.
1 DP Disable counting while in supervisor mode
0 The PMCn counters can be changed by hardware.
1 H the processor is in s1439rvisor mode (MSR[PR) is cleared), the counters are
not changed by hardware.
2
DU Disable counting while in user mode
0
The PMCn counters can be changed by hardware.
1
n
the processor
is
in user mode (MSR[PRJ
is
set}, the PMC counters are not
changed by hardware).
3 OMS Disable counting while MSR[PM)
Is
set
0
The PMCn counters can
be
changed by hardware.
1 H MSR[PM)
is
set, the PMCn counters are not changed
by
hardware.
4 OMA Disable counting while MSR[PMJ is
zero.
0 The PMCn counters can
be
changed by hardware.
1
n
MSR[PM)
is
cleared, the PMCn counters are
not
changed by hardware.
5
ENINT Enable performance monitor interrupt signaling.
0
Interrupt slgnating
is
disabled.
1 Interrupt signaling is enabled.
This
bit
is cleared by hardware when a performance monitor interrupt is signaled.
To reenable these interrupt signals, software must
set
this bit after servicing the
performance monitor Interrupt. This bit is cleared before passing control to the
operating system.
6
DISCOUNT Disable counting of PMC1
and
PMC2 when a performance monitor Interrupt
is
signaled (that is, ((PMCnlNTCONTROL= 1) & (PMCn[OJ = 1) & (ENINT = 1)) or
the occurrence of an enabled time
base
transition with ((INTONBITTRANS =1)
&
(ENINT = 1)).
0 Signaling a performance monitor Interrupt has no effect on the counting
status of PMC1 and PMC2.
1 Signaling a performance monitor interrupt prevents the PMC1 counter
from
changing. The PMC2 counter does not change H PMC2COUNTCTL = 0.
Because, a time-base signal could have occurred along with an enabled counter
negative condition, software should
always
reset INTONBITTRANS
to zero,
H the
value in INTONBITTRANS
was
a one.
Chapter 9. Performance
Monitor
9-7