Table of Contents
Advertisement
8.9 Processor State Signals
This section describes the 604's support for atomic update and memory through the use of
the
lwarx/stwcx.
opcode pair.
8.9.1 Support for the lwarx/stwcx. Instruction Pair
The Load Word
and
Reserve Indexed
(lwarx)
and the Store Word Conditional Indexed
(stwcx.)
instructions provide a means for atomic memory updating. Memory can be
updated atomically by setting a reservation on the load
and
checking that the reservation is
still valid before the store is perfonned. In the 604, the reservations are made on behalf of
aligned, 32-byte sections of the memory address space.
The
reservation (RSRV) output signal is driven synchronously with the bus clock and
reflects the status of the reservation coherency bit in the reservation address register (see
Chapter 3, "Cache and Bus Interface Unit Operation," for more information). See
Section 7.2.10.2, "Reservation (RSRV)-Output," for infonnation about timing.
8.1 O IEEE 1149.1-Compllant Interface
The 604 boundary-scan interface is a fully-compliant implementation of the IEEE 1149.1
standard This section describes the 604 IEEE 1149.l(JTAG) interface.
8.10.1 IEEE 1149.1 Interface Description
The 604 has five dedicated JTAG signals which are described in Table 8-11. The TDI and
TOO scan ports are used to scan instructions as well as data into the various scan registers
for JTAG operations.
The
scan operation is controlled by the test access port (TAP)
controller which in
turn
is controlled by the TMS input sequence. The scan data is latched
in at the rising edge of TCK.
Table 8-11. IEEE Interface Pin Descriptions
SlgnalName
Input/Output
WeakPullup
IEEE 1149.1 Function
Provided
TOI
Input
Yes
Serial
scan i'1)ut pin
TOO
Output
No
Serial
scan output
pin
TMS
Input
Yes
TAP oontroDer mode pin
TCK
Input
Yes
Scan clock
TFmT
Input
Yes
TAP controller reset
TRST is a JTAG optional signal which is used to reset the TAP controller asynchronously.
The TRST signal assures that the JTAG logic does not interfere with the nonnal operation
of the chip, and should
be
held asserted during normal operation. The remaining JTAG
signals are provided with internal pullup resistors,
and
may
be
left unconnected
8-52
PowerPC 604 RISC Micropl'OC8880r User's Manual
Advertisement
Chapters
Table of Contents
