Processor Identification Register (Pir) - IBM PowerPC 604 User Manual

ADDRESS
0 29 30 31
Figure 2·2. Instruction Address Breakpoint Register
The instruction address breakpoint register is used in conjunction with the instruction -
address breakpoint exception, which occurs when an attempt is made to execute an
instruction at an address specified in the IABR. The bits in the IABR are defined as shown
in Table 2-2.
Table 2-2. Instruction Address Breakpoint Register Bit Settings
Bit
Description
0-29
Word address to be compared
30
Breakpoint enabled. Setting this bit indicates that breakpoint cheeking is to be done.
31 Translation enabled. This bit is compared with the MSR(IR] bit. An IABR match is
signaled only if these bits also match.
The instruction that triggers the instruction address breakpoint exception is executed before
the exception handler is invoked. For more information about the IABR exception, see
Section 4.5.14, "Instruction Address Breakpoint Exception (Ox01300)."
The IABR can be accessed with the mtspr and mfspr instructions using the SPR number,
1010.
2.1.2.2 Processor Identification Register (PIR)
The processor identification register (PIR) is a 32-bit register that holds a processor
identification tag in the four least significant bits (PIR[28-31]). This tag is useful for
processor differentiation in multiprocessor system designs. In addition, this tag is used for
several direct-store bus operations in the form of a "bus traiisaction from" tag.
PIR
Ell
Reserved
m:::::1111:1::::::::11:1r:1:1:1:i:i:!~§i9.J:i::1:@1::1:P:@!B~:P::~o~@1:9:q:gjg)j@)mt1m:::::11::::1::::::::~::::::::1::::~1:1:::::1
PIO
I
0 27 28 31
Figure 2·3. Processor Identification Register
Chapter 2. PowerPC 604 Processor Programming Model
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