Address Transfer - IBM PowerPC 604 User Manual

8.3.2 Address Transfer
During the address transfer, the physical address and all attributes of the transaction are
transferred from the bus master to the slave device(s). Snooping logic may monitor the
transfer to enforce cache coherency; see discussion about snooping in Section 8.3.3,
"Address Transfer Termination."
The signals used in the address transfer include the following signal groups:
• Address transfer start signal: Transfer start (TS)
Note that extended address transfer start (XATS) signal is used for direct-store
operations and has no function for memory-mapped accesses; see Section 8.6,
"Direct-Store Operation."
• Address transfer signals: Address bus (AO-A31), address parity (APO-AP3), and
address parity error (APE)
• Address transfer attribute signals: Transfer type
(T~
TT4), transfer code (TCO-
TC2), transfer size (TSIZO-TSIZ2), transfer burst (TBST), cache inhibit (Cl), write-
through (WT), global (GBL), and cache set element (CSEO-CSEl)
Figure 8-6 shows that the timing for all of these signals, except TS and APE is identical. All
of the address transfer and address transfer attribute signals are combined into the ADDR
+
grouping in Figure 8-6. The TS signal indicates that the 604 has begun an address transfer
and that the address and transfer attributes are valid (within the context of a synchronous
bus). The 604 always asserts TS (or XATS for direct-store operations) coincident with
ABB.
As
an input, TS need not coincide with the assertion of ABB on the bus (that is, either
TS or XATS can be asserted with, or on a subsequent clock cycle after ABB is asserted; the
604 tracks this transaction correctly).
8-12
0
quatliG
i\..___..,_......,
TS"
'----~
.....
I
.}--~.......::i...,
I
XD1
I
ADDR+ I
I
artry_in
I
2
Figure 8-6. Address Bus Transfer
3 4
PowerPC 604 RISC Microprocessor User's Manual