IBM PowerPC 604 User Manual page 246

3. The following occurs in cycle 3:
- The first two integer instructions
(and
and or) enter the execute stages of the two
SCIUs. The two integer instructions decoded in cycle 2 (addc and subfc) are
dispatched without delay to the two SCIUs. The next pair of integer instructions
(xor and neg) is in decode stage and the final pair of integer instructions (add
and subf) is fetched from the second quad word in the instruction cache block.
- The fadd instruction enters execute stage in the FPU, vacating the dispatch
stage, allowing the fsub instruction to dispatch. The fmadd and fmsub
instructions are in decode stage, and the final pair of floating-point instructions
(fadds and fsubs) is fetched
4. The following occurs in cycle 4:
- In the SCIUs, the first two integer instructions complete execution and write
back their results, and the second pair of integer instructions (addc and subfc)
enters execute stage. The next pair of integer instructions (xor and neg) is held
in the dispatch stage because the fmsub instruction cannot dispatch.
- The fadd instruction is in the second of the three execute stages and fsub is in
the first. The fmadd instruction (6) is in the dispatch stage, which forces fmsub
to remain in the dispatch stage, similar to the situation in cycle 1 when two
floating-point instructions were ready for dispatch. Note that because of in-order
dispatch, the integer instructions (8 and 9) are also held in the dispatch stage
behind
the
fmsub instruction. The final pair of floating-point instructions enters
decode stage.
5. The following occurs in cycle 5:
- The first two integer instructions have completed, written back their results, and
vacated the pipeline. The second pair of integer instructions has executed and
vacated the execution stages, but must remain in the completion buff er until the
previous floating-point instructions can complete. The third pair of integer
instructions is allowed to dispatch, and the final pair of integer instructions is
held in the decode stage behind the previous floating-point instructions
(10and11).
- In the FPU, fadd is in the final execute stage, fsub is in the second stage, fmadd
is in the first, and fmsub is allowed to dispatch. Because instructions 7-9 occupy
the two available positions for instruction pairs in the dispatch unit, fadds and
fsubs are held in decode, again, forcing subsequent integer instructions to remain
in decode.
6. The following occurs in cycle 6:
6·20
- The second pair of integer instructions (4 and 5) remains in the completion buffer
waiting for the previous floating-point instructions
to
complete. The third pair of
integer instructions is in execute stage, and the final pair of integer instructions
is held in the dispatch stage behind the fsubs instruction.
PowerPC 604 RISC Microprocessor User's Manual