Load/Store Unit Instruction Timings - IBM PowerPC 604 User Manual

6.5.4 Load/Store Unit Instruction Timings
The execution of most load and store instructions is pipelined.
The
LSU has two pipeline
stages; the first stage is for effective address calculation, and MMU translation, and the
second stage is for accessing the data in the cache. Load instructions have a two-cycle
latency and one-cycle throughput, and store instructions have a two-cycle latency and
single-cycle throughput
The primary function of the LSU is to transfer data between the data cache and the result
bus, which routes data to the other execution units. The LSU supports the address
generation and all the data alignment to and from the data cache. As shown in Table 6-2,
the LSU also executes special instructions such as string transfers and cache control.
To improve execution performance, the LSU allows a load operation to be executed ahead
of pending store operations. All data dependencies introduced by this out-of-order
execution are resolved by the LSU. The.se dependencies arise when, in the instruction
stream, a store is followed by a load from the same address. If the load instruction is
speculatively executed before the store has modified the cache, incorrect data is loaded into
the rename registers. If the low-order 12 bits of the effective addresses are equal, the two
effective addresses may be aliases for the same physical address, in which case the load
instruction waits until the store data is written back to the cache, guaranteeing that the load
operation retrieves the correct data. -
The LSU provides hardware support for denormalization of floating-point numbers.
Within
the 604, all floating-point numbers are represented as double-precision numbers.
Denormalization can occur during a store floating-point single instruction, when the
double-precision number is converted to a single-precision number.
A block diagram of the load/store unit is shown in Figure 6-17. The unit is composed of:
reservation stations, an address calculation block, data alignment blocks, load queues, and
store queues.
Chapter 6. Instruction Timing 6-39