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Table 3-4. Response to Bus Transactions (Continued)
Transaction
Response
XFERDATA
XFERDATA read and write operations are bus transactions that result from execution
of
the eclwx or ecowx instructions, respectively. These instructions assist certain adapter
types (especially displays) to make high-speed data transfers. They do this by
calculating an effective address, translating
it,
and presenting the resulting physical
address to the adapter.
The XFERDATA read and write operations transfer a word of data to or from the
processor, respectively. They also present the 4-bit resource ID (RID) field, using the
concatenation
of
the bits TBST
II
TSIZ[~).
These transactions are unique in the sense
that the address that is transferred does not select the slave device;
it is
simply being
passed to the slave device for use in a subsequent transaction. Rather, the RID bits are
used to select among the slave devices.
Ahhough the intent of these instructions is that the slave device that is selected
by
the
RID bits wm use the address that is transferred in a subsequent data transfer, the exact
nature of this data transfer is not defined by 604
bus
specifications. It is a private
transfer that can be defined
by
the system like
any
other direct memory access.
3.9. 7 Enveloped High-Priority Cache Block Push Operation
If the 604 bas a read operation outstanding on the bus and another pipelined bus operation
hits against a modified block, the 604 provides a high-priority push operation. This
transaction can be enveloped within the address and data tenures of a read operation. This
feature prevents deadlocks in system organizations that support multiple memory-mapped
buses. More specifically, the 604 internally detects the scenario where one or more load
requests are outstanding and the processor has pipelined a write operation on top of the
load Normally, when the data bus is granted to the 604, the resulting data bus tenure is used
for the load operation.
The enveloped high-priority cache block push feature defines a bus signal, the data bus
write only qualifier (DBWO), which, when asserted with a qualified data bus grant,
indicates that the resulting data tenure should be used for the first store operation instead.
If no store operation is pending, the first read operation is performed If no write operation
is pending, the 604 can perform a read operation. This signal is described in detail in
Section 8.11, "Using Data Bus Write Only." Note that the enveloped copy-back operation
is an internally pipelined bus operation.
3.9.8 Bus Operations Caused by Cache Control Instructions
Table 3-5 provides an overview of the bus operations initiated by cache control
instructions. Note that Table 3-5 assumes that the WIM bits are set to 001; that is, since the
cache is operating in write-back mode, caching is permitted and coherency is enforced.
3-22
PowerPC 604 RISC Microprocessor User's Manual
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