IBM PowerPC 604 User Manual page 437

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INDEX
Multiple-precision shifts, 2-30
N
Nap mode, 4-21
No-DR1RY mode, 8-48, 8-49, 8-50
0
OEA
cache operation, 3-1
definition, 1-19
exception mechanism, 4-1
memory management specifications, 5-1
registers, 2-5
Operand conventions, 2-16
Operand placement and perfonnance, 2-19
Operating environment architecture, see OEA
Optional instructions, A-39
p
Page address translation
page address translation flow, 5-27
page size, 5-20
selection of page address translation, 5-9, 5-16
1LB organization, 5-25
Page history status
cases of debt and dcbtst misses, 5-21
Making R and C bit updates to page tables, 5-33
Rand C bit recording, 5-12, 5-21-5-24
Rand C bit updates, 5-12, 5-33
Page tables
page table updates, 5-33
Perfonnance considerations, memory, 6-12
Perfonnance monitor
event counting, 9-8
perfonnance monitor facility, 1-35
perfonnance monitor SPRs, 9-3
perfonnance monitoring interrupt, 9-2
perfonnance monitoring mechanism, 4-20
purposes, 9-1
Physical address generation
memory management unit, 5-1
Pipeline
completion stage, 6-11
decode stage, 6-9
dispatch stage, 6-9
exe.cutestage,6-10
fetch stage, 6-8
instruction timing, definition, 6-1
pipeline diagram, 6-6
pipeline stages, 6-7
pipeline structures,
6-5
write-back stage, 6-12
lndex-6
PIR (processor identification register), 2-8, 2-9
PLL configuration, 7-31
PMCl and PMC2 registers, 2-8, 2-13, 9-1, 9-3
Postdispatch seriali7.ation mode, 6-34
Power management
nap mode, 4-21
overview, l-35
POW bit, 4-21
PowerPC architecture
features used in 604, 1-20
instruction list, A-1, A-10, A-18, A-28, A-39
levels of implementation, 1-19
operating environment an:hitecture, xxii
user instruction set architecture, xxi
virtual environment architecture, xxi
Priorities
exception priorities, 4-5
Process switching, 4-11
Processor configuration
HALTED, 7-29
L2_INT, 7-28
RSRV, 7-28
RUN,7-29
TBEN, 7-28
Processor control instructions, 2-46, 2-48, 2·52
Program exception, 4-17
Program order, 6-2
Programming tips, 6-43
Protection of memory areas
direct-store interface protection, 5-35
no-execute protection, 5-14
options available, 5-11
protection violations, 5-16
PTEs (page table entries)
page table updates, 5-33
PVR (processor version register), 2-6
Q
Qualified data bus grant, 8-7, 8-20
Qualified snoop request, 3-19
R
Read operation, 3-20
Read-atomic operation, 3-20
Read-with-intent-to-modify operation, 3-20
Read-with-no-intent-to-cache operation, 3-21
Real address (RA), see physical address generation
Real addressing mode (translation disabled)
data accesses, 5-10, 5-12,5-20
instruction accesses, 5-10, 5-12, 5-20
support for real addressing mode, 5-2
PowerPC 604 RISC MicroproC888or User's Manual