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3.8.2 Instruction Synchronize (isync)
The isyne instruction causes the 604 to purge its instruction buffers and fetch the next
sequential instruction.
3.8.3 Data Cache Block Touch (debt) and
Data Cache Block Touch for Store (dcbtst)
The Data Cache Block Touch
(debt) and Data Cache Block Touch for Store (debtst)
instructions provide potential system performance improvement through the use of
software-initiated prefetch hints. The 604 treats these instructions identically. Note that
PowerPC implementations are not required to take any action based on the execution of this
instruction, but they may choose to prefetch the cache block corresponding to the effective
address into their cache. The 604 fetches the data into the cache when the address hits in
the TLB or the BAT, is permitted load access from the addressed page, is not directed to a
direct-store segment, and is directed at a cacheable page. Otherwise, the 604 treats these
instructions as no-ops.
Regarding MESI cache coherency, the data brought into the cache as a result of these
instructions is validated in the same manner that a load instruction would
be
(that is, if no
other bus participant has a copy, it is marked as exclusive; otherwise it is marked as shared).
The memory reference of a
debt instruction causes the reference bit to be set.
Note also that the successful execution of the
debt instruction affects the state of the TLB
and cache LRU bits as defined by the LRU algorithm.
3.8.4 Data Cache Block Set to Zero (dcbz)
As defined in the VEA, when the
debz instruction is executed the effective address is
computed, translated, and checked for protection violations. If the 604 does not already
have exclusive access to this cache block, it presents a kill operation onto the 604 bus-a
kill operation instructs all other processors to invalidate copies of the cache block that may
reside in their caches. After it has exclusive access to the cache block, the 604 writes all
zeros into the cache block. In the event that the 604 already has exclusive access, it
immediately writes all zeros into the cache block. If the addressed block is within a
noncacheable or a write-through page, or if the cache is locked or disabled, an alignment
exception occurs.
3.8.5 Data Cache Block Store (dcbst)
As defined in the VEA, when a Data Cache Block Store
(debst) instruction is executed, the
effective address is computed, translated, and checked for protection violations. If the 604
does not have modified data in this block, the 604 broadcasts a clean operation onto the bus.
If modified (dirty) data is associated with the cache block, the processor pushes the
modified data out of the cache and into the memory queue for future arbitration onto the
604 bus. In this situation, the cache block is marked as exclusive. Otherwise this instruction
is treated as a no-op.
Chapter 3. Cache and Bus Interface Unit Operation
3-17
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