Instruction Timing - IBM PowerPC 604 User Manual

Chapter 6
Instruction Timing
This chapter describes instruction prefetch and execution through all of the execution units
of the PowerPC 604 microprocessor. It also provides examples of instruction sequences
showing concurrent execution and various register dependencies to illustrate timing
interactions.
6.1 Terminology and Conventions
This section describes terminology and conventions used in this chapter. This section
defines terms used in this chapter.
• Stage-An element in the pipeline at which certain actions are performed, such as
decoding the instruction, performing an arithmetic operation, and writing back the
results. A stage typically takes a cycle to perform its operation; however, some
stages are repeated (a double-precision floating-point multiply, for example). When
this occurs, an instruction immediately following it in the pipeline is forced to stall
in its cycle.
In some cases, an instruction may also occupy more than one stage
simultaneously-for example, instructions may complete and write back their
results in the same cycle.
After an instruction is fetched, it can always be defined as being in one or more
stages.
• Pipeline-In the context of instruction timing, the term pipeline refers to the
interconnection of the stages. The events necessary to process an instruction are
broken into several cycle-length
tasks
to
allow work to be performed on several
instructions simultaneously-analogous to an assembly line. As an instruction is
processed, it passes from one stage to the next. When it does, the stage becomes
available for the next instruction.
Although an individual instruction may take many cycles to complete (the number
of cycles is called instruction latency}, pipelining makes it possible to overlap the
processing so that the throughput (number of instructions completed per cycle) is
greater than if pipelining were not implemented.
Chapter &. Instruction Timing
6-1