IBM PowerPC 604 User Manual page 55

• The decrementer register (DEC) is a 32-bit decrementing counter that provides a
mechanism for causing a decrementer exception after a programmable delay. In the
604, the decrementer frequency is 1/4th of the bus clock frequency (as is the time
base_ frequency).
• The 32-bit SDRl register specifies the location and page table format used in
logical-to-physical address translation for pages.
• The machine status save/restore register 0 (SRRO) is a 32-bit register that is used by
the 604 for saving the address of the instruction that caused the exception, and the
address to return to when a Return From Interrupt
(rfi)
instruction is executed.
• The machine status save/restore register 1 (SRRl) is a 32-bit register used to save
machine status on exceptions and to restore machine status when an rfi instruction
is executed.
• SPRGO-SPRG3 registers are 32-bit registers provided for operating system use.
• The external access register
(EAR)
is a 32-bit register that controls access to the
external control facility through
the
External Control In Word Indexed ( eciwx) and
External Control Out Word Indexed (ecowx) instructions.
• The processor version register (PVR) is a 32-bit, read-only register that identifies the
version (model) and revision level of the PowerPC processor.
• The time base registers
(TBL
and TBU) together provide a 64-bit time base register.
The registers are implemented as a 64-bit counter, with the least-significant bit being
the
most frequently incremented. The PowerPC architecture defines that the time
base frequency be provided as a subdivision of the processor clock frequency. In the
604,
the time base frequency is l/4th of the bus clock frequency (as is the
decrementer frequency). Counting is enabled by the Time Base Enable signal
(TBEN).
• Block address translation (BAT) registers-The PowerPC architecture defines 16
BAT registers, divided into four pairs of data BATs (DBATs) and four pairs of
instruction BATs (IBATs).
The 604 includes the following registers not defined by
the
PowerPC architecture:
• lnstrUction address breakpoint register (IABR)-This register can be used to cause
a breakpoint exception to occur if a specified instruction address is encountered.
• Data address breakpoint register (DABR)-This register can
be
used to cause a
breakpoint exception to occur if a specified data address is encountered
• Hardware implementation-dependent register 0 (HIDO)-This register is used to
control various functions within the 604, such as enabling checkstop conditions, and
locking, enabling, and invalidating the instruction and data caches.
• .Processor identification register (PIR)-The PIR is a supervisor-level register that
has a right-justified, four-bit field that holds a processor identification tag used to
identify a particular
604.
This tag is used to identify the processor in multiple-master
implementations.
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PowerPC 604 RISC Micropr0C8880r User's Manual