Mmu Overview - IBM PowerPC 604 User Manual

The MMUs, together with the exception processing mechanism, provide the necessary
support for the operating system to implement a paged virtual memory environment and for
enforcing protection of designated memory areas. Exception processing is described in
Chapter 4, "Exceptions." Section 4.3, "Exception Processing," describes the MSR, which
controls some of the critical functionality of the MMUs.
5.1 MMU Overview
The 604 implements the memory management specification of the PowerPC OEA for
32-bit implementations. Thus, it provides 4 Gbytes of effective address space accessible to
supervisor and user programs with a 4-Kbyte page size and 256-Mbyte segment size. In
addition, the MMUs of 32-bit PowerPC processors use an interim virtual address (52 bits)
and hashed page tables in the generation of 32-bit physical addresses. PowerPC processors
also have a BAT mechanism for mapping large blocks of memory. Block sizes range from
128 Kbyte to 256 Mbyte and are software-programmable.
Basic features of the 604 MMU implementation defined by the OEA are as follows:
• Support for real addressing mode-Logical-to-physical address translation can be
disabled separately for data and instruction accesses.
• Block address translation-Each of the BAT array entries (four IBAT entries and
four DBAT entries) provides a mechanism for translating blocks as large as
256 Mbytes from the 32-bit effective address space into the physical memory space.
This can be used for translating large address ranges whose mappings do not change
frequently.
• Direct-store segments-If the T bit in the indexed segment register is set for any
load or store request, this request accesses a direct-store segment; bus activity is
different and the memory space used has different characteristics with respect to
how it can be accessed The address used on the bus consists of bits from the EA and
the segment register.
• Segmented address translation-The 32-bit effective address is extended to a 52-bit
virtual address by substituting 24 bits of upper address bits from the segment
register, for the 4 upper bits of the EA, which are used as an index into the segment
register. This 52-bit virtual address space is divided into 4-Kbyte pages, each of
which can be mapped to a physical page.
The 604 also provides the following features that are not required by the PowerPC
architecture:
5-2
• Separate translation lookaside buffers (TLBs)-The 128-entry, two-way set
associative ITLBs and DTLBs keep recently-used page address translations on-chip.
• Table search operations performed in hardware-The 52-bit virtual address is
formed and the MMU attempts to fetch the PTE, which contains the physical
address, from the appropriate TLB on-chip. If the translation is not found in a TLB
(that is, a TLB miss occurs), the hardware performs a table search operation (using
a hashing function) to search for the PTE.
PowerPC 604 RISC Microprocessor User's Manual