Data Bus Tenure; Data Bus Arbitration - IBM PowerPC 604 User Manual

8.4 Data Bus Tenure
This section describes the data bus arbitration, transfer, and tennination phases defined by
the 604 memory access protocol. The phases of the data tenure are identical to those of the
address tenure, underscoring the symmetry in the control of the two buses.
8.4.1 Data Bus Arbitration
Data bus arbitration uses the data arbitration signal group-DBG, DBWO, and DBB.
Additionally, the combination of TS or XATS and TTO-TT4 provides information about
the data bus request to external logic.
The TS signal is an implied data bus request from the 604; the arbiter must qualify TS with
the transfer type (TT) encodings to determine if the current address transfer is an address-
only operation, which does not require a data bus transfer (see Figure 8-7). H the data bus
is needed, the arbiter grants data bus mastership by asserting the DBG input to the 604. As
with the address-bus arbitration phase, the 604 must qualify the DBG input with a number
of input signals before assuming bus mastership, as shown in Figure 8-8.
0
2
drtry
lttltlttftltlf
I I
I I
I I
qua/
15liG I I
I I
l5lm"
I I
I I
Figure 8-8. Data Bus Arbitration
I
I
3
I I
I I
I I
I I
A qualified data bus grant can be expressed as the following:
QDBG = DBG asserted while DBB, DRTRY, and ARTRY (associated with the data
bus operation) are negated.
When a data tenure overlaps with its associated address tenure, a qualified ARTRY
assertion coincident with a data bus grant signal does not result in data bus mastership
(DBB is not asserted). Otherwise, the 604 always asserts DBB on the bus clock cycle after
recognition of a qualified data bus grant. Since the 604 can pipeline transactions, there may
8-20
PowerPC 604 RISC Microprocessor User's Manual