Data Transfer Signals; Data Bus (Dho-Dh31, Dlo-Dl31) - IBM PowerPC 604 User Manual

7.2.7 Data Transfer Signals
Like the address transfer signals, the data transfer signals are used to transmit data and to
generate and monitor parity for the data transfer. For a detailed description of how the data
transfer signals interact, see Section 8.4.3, "Data Transfer."
7 .2. 7 .1 Data Bus (DHO-DH31, DLO-DL31)
The data bus (DHO-DH31 and DLO-DL31) consists of 64 signals that are both input and
output on the 604. Following are the state meaning and timing comments for the DH and
DLsignals.
State Meaning The data bus has two halves-data bus high (DH) and data bus low
(DL). See Table 7-4 for the data bus lane assignments. Direct-store
operations use DH exclusively (that is, there are no 64-bit, 1/0
transfers).
Timing Comments The data bus is driven once for noncached transactions and four
times for cache transactions (bursts).
Table 7-4. Data Bus Lane Assignments
Data Bus Signals Byte Lane
DHO-DH7
0
DH8-DH15 1
DH16-DH23 2
DH24-DH31 3
DLO-DL7
4
DL8-DL15 5
DL16-DL23
6
DL24-DL31
7
7.2.7.1.1 Data Bus (DHO-DH31, DLO-DL31)-0utput
Following are the state meaning and timing comments for the DH and DL output signals.
State Meaning Asserted/Negated-Represents the state of data during a data write.
Byte lanes not selected for data transfer will not supply valid data.
Timing Comments Assertion/Negation-Initial beat coincides with DBB and, for
bursts, transitions on the bus clock cycle following each assertion of
TA.
7-20
High Impedance-Occurs on the bus clock cycle after the final
assertion of TA.
PowerPC 604 RISC Microprocessor User's Manual