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Chapter 8
System Interface Operation
This chapter describes the PowerPC 604 microprocessor bus interface and its operation. It
shows how the 604 signals, defined in Chapter 7, "Signal Descriptions," interact to perform
address and data transfers.
8.1 PowerPC 604 Microprocessor System Interface
Overview
The system interface prioritizes requests for bus operations from the instruction and data
caches, and performs bus operations per the 604 bus protocol. It includes address register
queues, prioritization logic, and the bus control unit. The system interface latches snoop
addresses for snooping in the data cache and in the address register queues, and snoops for
direct-store reply operations and for reservations controlled by the Load Word and Reserve
Indexed (lwarx) and Store Word Conditional Indexed (stwcx.) instructions. The interface
allows two level of pipelining; that is, with certain restrictions discussed later, there can
be
three outstanding transactions at any given time. Accesses are prioritized with load
operations preceding store operations.
Instructions are automatically fetched from the memory system into the instruction unit
where they are dispatched to the execution units at a peak rate of four instructions per clock.
Conversely, load and store instructions explicitly specify the movement of operands to and
from the integer and floating-point register files and the memory system.
When the 604 encounters an instruction or data access, it calculates the logical address
(effective address in the architecture specification) and uses the low-order address bits
to
check for a hit in the on-chip, 16-Kbyte instruction and data caches. During cache lookup,
the instruction and data memory management units (MMUs) use the higher-order address
bits to calculate the virtual address, from which they calculate the physical address (real
address in the architecture specification). The physical address bits are then compared with
the corresponding cache tag bits to determine if a cache hit occurred. If the access misses
in the corresponding cache, the physical address is used to access system memory.
In addition to the loads, stores, and instruction fetches, the 604 performs hardware table
search operations following TLB misses, cache cast-out operations when least-recently
Chapter 8. System Interface Operation
8-1
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