Steps For Exception Processing; Setting Msr[Ri] - IBM PowerPC 604 User Manual

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• A machine check exception can occur only if the machine check enable bit,
MSR[ME], is set. If MSR[ME] is cleared, the processor goes directly into checkstop
state when a machine check exception condition occurs. Individual machine check
exceptions can be enabled and disabled through bits in the HIDO register, which is
described in Table 4-7.
• System reset exceptions cannot
be
masked
4.3.2 Steps for Exception Processing
After it is determined that the exception can be taken (by confirming that any instruction-
caused exceptions occurring earlier in the instruction stream have been handled, and by
confinning that the exception is enabled for the exception condition), the processor does
the following:
1.
The machine status save/restore register 0 (SRRO) is loaded with an instruction
address that depends on the type of exception. See the individual exception
description for details about how this register is used for specific exceptions.
2. Bits 1-4 and 10-15 of SRRl are loaded with information specific to the exception
type.
3. Bits 5-9and16-31 of SRRl are loaded with a copy of the corresponding bits of the
MSR. Note that depending on the implementation, reserved bits may not
be
copied.
4. The MSR is set as described in Table 4-3. The new values take effect beginning with
the fetching of the first instruction of the exception-handler routine located at the
exception vector address.
Note that MSR[IR] and MSR[DR] are cleared for all exception types; therefore,
address translation is disabled for both instruction fetches and data accesses
beginning with the first instruction of the exception-handler routine.
5. Instruction fetch and execution resumes, using the new MSR value, at a location
specific to the exception
type.
The location is determined by adding the exception's
vector (see Table 4-2) to the base address determined by MSR[IP].
If
IP is cleared,
exceptions are vectored to the physical address
OxOOOn _ nnnn. If
IP is set, exceptions
are vectored to the physical address OxFFFn _ nnnn. For a machine check exception
that occurs when MSR[ME]
=
0 (machine check exceptions are disabled), the
checkstop state is entered (the machine stops executing instructions). See
Section 4.5.2, "Machine Check Exception (Ox00200)."
4.3.3 Setting MSR[RI]
The operating system should handle MSR[RI] as follows:
• In the machine check and system reset exceptions-If SRRl [RI] is cleared, the
exception is not recoverable. If it is set, the exception is recoverable with respect to
the processor.
4·10 PowerPC 604 RISC Microprocessor User's Manual