Address Bus Tenure; Address Bus Arbitration - IBM PowerPC 604 User Manual

8.3 Address Bus Tenure
This section describes the three phases of the address tenure-address bus arbitration,
address transfer, and address tennination.
8.3.1 Address Bus Arbitration
When the 604 needs access to the external bus and does not have a qualified bus grant, it
asserts bus request (BR) until it is granted mastership of the bus and the bus is available
(see Figure 8-4). The external arbiter must grant master-elect status to the potential master
by asserting the bus grant (BG) signal. The 604 requesting the bus detennines that the bus
is available when the ABB input is negated. When the address bus is not busy (ABB input
is negated), BG is asserted and the address retry (ARTRY) input is negated, and was
negated the previous cycle, the 604 has what is referred to as a qualified bus grant. The 604
assumes address bus mastership by asserting ABB when it receives a qualified bus grant.
Logical Bus Clock
ne8d_bus
1
Im"
I
'bg I
qua/BG
I
• 1
0
AmJ'--~~~..__~~---,
.........
I
-....--~~~
Figure 8·4. Address Bus Arbitration
External arbiters must allow only one device at a time to be the address bus master.
Implementations in which no other device can be a master, BG can be grounded (always
asserted) to continually grant mastership of the address bus to the 604.
If the 604 asserts BR before the external arbiter asserts BG, the 604 is considered to
be
unparked, as shown in Figure 8-4. Figure 8-5 shows the parked case, where a qualified bus
grant exists on the clock edge following a need_ bus condition. Notice that the two bus clock
cycles required for arbitration are eliminated if the 604 is parked, reducing overall memory
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PowerPC 604 RISC Microprocessor User's Manual