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In Figure 8-6, the address transfer occurs during bus clock cycles 1 and 2 (arbitration
occurs in bus clock cycle 0 and the address transfer is terminated in bus clock 3). In this
diagram, the address bus termination input, AACK, is asserted to the 604 on the bus clock
following assertion of TS (as shown by the dependency line). This is the minimum duration
of the address transfer for the 604; the duration can be extended by delaying the assertion
of AACK for one or more bus clocks.
8.3.2.1 Address Bus Parity
The 604 always generates one bit of correct odd-byte parity for each of the four bytes of
address when a valid address is on the bus. The calculated values are placed on the APO-
AP3 outputs when the 604 is the address bus master. If the 604 is not the master, TS and
GBL are asserted together, and the transaction type is one that the 604 snoops (qualified
condition for snooping memory operations), the calculated values are compared with the
APO-AP3 inputs. If there is an error, the APE output is asserted. If HID0[2] is set to 1, a
parity error will cause a machine check if the MSR[ME] bit is set, or will cause a checkstop
if the MSR[ME] bit is cleared. If HID0[2] is cleared to 0, then no action is taken. In either
case, the APE signal will be asserted if even parity is detected. For more information about
checkstop conditions, see Chapter 4, "Exceptions."
8.3.2.2 Address Transfer Attribute Signals
The transfer attribute signals include several encoded signals such as the transfer type
(TTO-TT4) signals, transfer burst (TBST) signal, transfer size (TSIZO-TSIZ2) signals, and
transfer code (TCO-TC2) signals. Section 7 .2.4, "Address Transfer Attribute Signals,"
describes the encodings for the address transfer attribute signals. Note that TTO-TT4,
TBST, and TSIZO-TSIZ2 have alternate functions for direct-store operations; see
Section 8.6, "Direct-Store Operation."
8.3.2.2.1 Transfer Type {TTO-TT4) Signals
Snooping logic should fully decode the transfer type signals if the GBL signal is asserted.
Slave devices can sometimes use the individual transfer type signals without fully decoding
the group. For a complete description of the encoding for TTO-TT4 signals, refer
to
Table 7-1.
8.3.2.2.2 Transfer Size (TSIZO-TSIZ2) Signals
The transfer size signals (TSIZO-TSIZ2) indicate the size of the requested data transfer as
shown in Table 8-2. The TSIZO-TSIZ2 signals may be used along with TBST and A29-
A31 to determine which portion of the data bus contains valid data for a write transaction
or which portion of the bus should contain valid data for a read transaction. Note that for a
burst transaction (as indicated by the assertion of TBST) TSIZO-TSIZ2 are always set to
ObOlO. Therefore, if the TBST signal is asserted (except in cases of direct-store operations,
or operations involving the use of eciwx or ecowx instructions), the memory system should
transfer a total of eight words (32 bytes), regardless of the TSIZO-TSIZ2 encoding.
Chapter 8. System Interface Operation
8-13
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