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IBM Manuals
Computer Hardware
PowerPC 405GP
User manual
IBM PowerPC 405GP User Manual
Embedded processor
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Figures
About this Book
Who Should Use this Book
Conventions
Part I. Introducing the PPC405GP Embedded Processor
Chapter 1. Overview
PPC405GP Features
Bus and Peripheral Features
Figure 1-1. PPC405GP Block Diagram
Powerpc Processor Core Features
Powerpc Architecture
The PPC405GP as a Powerpc Implementation
RISC Processor Core Organization
Instruction and Data Cache Controllers
Instruction Cache Unit
Data Cache Unit
Memory Management Unit
Timer Facilities
Debug
Development Tool Support
Debug Modes
Processor Core Interfaces
Processor Local Bus
Device Control Register Bus
Clock and Power Management
Jtag
Interrupts
On-Chip Memory
Processor Core Programming Model
Data Types
Processor Core Register Set Summary
General Purpose Registers
Special Purpose Registers
Machine State Register
Condition Register
Device Control Registers
Chapter 2. On-Chip Buses
Processor Local Bus
PLB Features
PLB Masters and Slaves
PLB Master Assignments
Table 2-1. PPC405GP PLB Agents as Masters and Slaves
PLB Transfer Protocol
Table 2-2. Registers Controlling PLB Master Priority Assignments
Overlapped PLB Transfers
Figure 2-1. Overlapped PLB Transfers
PLB Arbiter Registers
PLB Arbiter Control Register (PLBO_ACR)
PLB Error Address Register (PLBO_BEAR)
Table 5-1
PLB Error Status Register (PLBO_BESR)
PLB to OPB Bridge Registers
Bridge Error Address Register (POBO_BEAR)
Bridge Error Status Registers (POBO_BESRO-POBO_BESR1)
Table 2-4. PLB Arbiter Registers
On-Chip Peripheral Bus
OPB Features
OPB Master Assignments
OPB Arbiter Registers
OPB Arbiter Control Register (OPBAO_CR)
Table 2-6. PLB Arbiter Registers
OPB Arbiter Priority Register (OPBAO_PR)
Part II. the PPC405GP Rise Processor
Chapter 3. Programming Model
User and Privileged Programming Models
Memory Organization and Addressing
Physical Address Map
Table 3-1. PPC405GP Address Space
Storage Attributes
Registers
Figure 3-1. PPC405GP Programming Model-Registers
General Purpose Registers (RO-R31)
Special Purpose Registers
Figure 3-2. General Purpose Registers (RO-R31)
Count Register (CTR)
Link Register (LR)
Fixed Point Exception Register (XER)
Figure 3-3. Count Register (CTR)
Figure 3-4. Link Register (LR)
Figure 3-5. Fixed Point Exception Register (XER)
Table 3-3. XER[CA] Updating Instructions
Special Purpose Register General (SPRGO-SPRG7)
Table 3-4. XER[SO,OV] Updating Instructions
Processor Version Register (PVR)
Condition Register (CR)
Figure 3-7. Processor Version Register (PVR)
CR Fields after Compare Instructions
Figure 3-8. Condition Register (CR)
The CRO Field
The Time Base
Machine State Register (MSR)
Figure 3-9. Machine State Register (MSR)
Table 3-5. Time Base Registers
Device Control Registers
Directly Accessed Dcrs
Figure 7-3. Chip Control Register
Table 3-6. Directly Accessed Dcrs
Indirectly Accessed Dcrs
Indirect Access of SDRAM Controller Dcrs
Table 3-7. SDRAM Controller DCR Usage
Table 3-8. Offsets for SDRAM Controller Registers
Indirect Access of External Bus Controller Dcrs
Table 3-9. External Bus Controller DCR Usage
Table 3-10. Offsets for External Bus Controller Registers
Indirect Access of Decompression Controller Dcrs
Table 3-11. Decompression Controller DCR Usage
Table 3-12. Offsets for Decompression Controller Registers
Memory-Mapped Input/Output Registers
Directly Accessed MMIO Registers
Table 3-13. Directly Accessed MMIO Registers
Figure 19-15. Mode Register
Indirectly Accessed MMIO Registers
Table 3-15. PCI Configuration Registers
Data Types and Alignment
Figure 3-10. PPC405GP Data Types
Alignment for Storage Reference and Cache Control Instructions
Alignment and Endian Operation
Summary of Instructions Causing Alignment Exceptions
Byte Ordering
Table 3-16. Alignment Exception Summary
Structure Mapping Examples
Big Endian Mapping
Little Endian Mapping
Support for Little Endian Byte Ordering
Endian (E) Storage Attribute
Fetching Instructions from Little Endian Storage Regions
Accessing Data in Little Endian Storage Regions
Powerpc Byte-Reverse Instructions
Figure 3-11. Normal Word Load or Store (Big Endian Storage Region)
Figure 3-12. Byte-Reverse Word Load or Store (Little Endian Storage Region)
Instruction Processing
Figure 3-13. Byte-Reverse Word Load or Store (Big Endian Storage Region)
Figure 3-14. Normal Word Load or Store (Little Endian Storage Region)
Branch Processing
Unconditional Branch Target Addressing Options
Conditional Branch Target Addressing Options
Conditional Branch Condition Register Testing
BO Field on Conditional Branches
Table 3-17. Bits of the BO Field
Branch Prediction
Table 3-18. Conditional Branch BO Field
Speculative Accesses
Speculative Accesses in the PPC405GP
Prefetch Distance down an Unresolved Branch Path
Prefetch of Branches to the CTR and Branches to the LR
Preventing Inappropriate Speculative Accesses
Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction
Fetching Past Tw or Twi Instructions
Fetching Past an Unconditional Branch
Suggested Locations of Memory-Mapped Hardware
Table 3-19. Example Memory Mapping
Privileged Mode Operation
MSR Bits and Exception Handling
Privileged Instructions
Privileged Sprs
Privileged Dcrs
Synchronization
Context Synchronization
Executio!,,! Synchronization
Storage Synchronization
Instruction Set
Table 3-21. PPC405GP Instruction Set Summary
Instructions Specific to IBM Powerpc Embedded Processors
Storage Reference Instructions
Table 3-22. Implementation-Specific Instructions
Table 3-23. Storage Reference Instructions
Arithmetic Instructions
Table 3-24. Arithmetic Instructions
Logical Instructions
Compare Instructions
Table 3-25. Multiply-Accumulate and Multiply Halfword Instructions
Table 3-26. Logical Instructions
Table 3-27. Compare Instructions
Branch Instructions
CR Logical Instructions
Rotate Instructions
Table 3-28. Branch Instructions
Table 3-29. CR Logical Instructions
Table 3-30. Rotate Instructions
Shift Instructions
Cache Management Instructions
Interrupt Control Instructions
Table 3-31. Shift Instructions
Table 3-32. Cache Management Instructions
Table 3-33. Interrupt Control Instructions
TLB Management Instructions
Processor Management Instructions
Extended Mnemonics
Table 3-34. TLB Management Instructions
Table 3-35. Processor Management Instructions
Chapter 4. Cache Operations
ICU Organization
Table 4-1. Instruction Cache Organization
Figure 4-1. Instruction Flow
Instruction Cachability Control
Instruction Cache Synonyms
ICU Coherency
DCU Organization
DCU Operations
Table 4-2. Data Cache Organization
DCU Write Strategies
DCU Load and Store Strategies
Data Cachability Control
DCU Coherency
Cache Instructions
ICU Instructions
DCU Instructions
Cache Control and Debugging Features
Figure 4-2. Core Configuration Register
CCRO Programming Guidelines
Figure 4-3. Instruction Cache Debug Data Register (ICDBDR)
DCU Debugging
DCU Performance
Pipeline Stalls
Cache Operation Priorities
Table 4-3. Priority Changes with Different Data Cache Operations
Simultaneous Cache Operations
Sequential Cache Operations
Chapter 5. On-Chip Memory
OCM Programming Guidelines
Store Data Bypass Behavior and Memory Coherency
Registers
Table 5-2. OCM Dcrs
OCM Instruction-Side Control Register (OCMO_ISCNTL)
OCM Data-Side Address Range Compare Register (OCMO_DSARC)
Chapter 6. Memory Management
MMU Overview
Address Translation
Translation Lookaside Buffer (TLB)
Unified TLB
Figure 6-1. Effective to Real Address Translation Flow
TLB Fields
Page Identification Fields
Translation Field
Table 6·1. TLB Fields Related to Page Size
Access Control Fields
Storage Attribute Fields
Shadow Instruction TLB
ITLB Accesses
Shadow Data TLB
DTLB Accesses
Shadow TLB Consistency
Figure 6-3. ITLB/DTLB/UTLB Address Resolution
TLB-Related Interrupts
Data Storage Interrupt
Instruction Storage Interrupt
Data TLB Miss Interrupt
Instruction TLB Miss Interrupt
TLB Management
TLB Search Instructions (Tlbsxltlbsx.)
TLB Invalidate Instruction (Tibia)
TLB Sync Instruction (Tlbsync)
Recording Page References and Changes
Access Protection
Access Protection Mechanisms in the TLB
General Access Protection
Execute Permissions
Write Permissions
Zone Protection
Figure 6-5. Zone Protection Register (ZPR)
Access Protection for Cache Control Instructions
Table 6-2. Protection Applied to Cache Control Instructions
Access Protection for String Instructions
Real-Mode Storage Attribute Control
Storage Attribute Control Registers
Data Cache Write-Through Register (DCWR)
Figure 6-6. Generic Storage Attribute Control Register
Data Cache Cachability Register (DCCR)
Instruction Cache Cachability Register (ICCR)
Storage Guarded Register (SGR)
Storage User-Defined 0 Register (SUOR)
Part III. PPC405GP System Operations
Chapter 7. Clocking
PLL Overview
Figure 7-1. PPC405GP Clocking
Input Reference Clock (Sysclk)
External Clock Strapping Setup
Table 7-1. Clock Strapping Values
Sample Clock Ratios
Table 7-2. PLL Tuning Settings
Table 7-3. Possible Clocking Ratios for Reference Clock of 33.3Mhz
Table 7-4. Possible Clocking Ratios for Reference Clock of 25Mhz
PCI Clocking
PCI Clocks
PCI Adapter Applications
Table 7-6. Example Synchronous PCI Clock Frequencies in Asynchronous Mode
Serial Port Clocking
Clocking Registers
Table 7-7. Clocking Control Registers
PLL Mode Register (CPCO_PLLMR)
Chip Control Register 0 (CPCO_CRO)
Reset and Initialization
Reset Signals
Reset Types
Core Reset
Chip Reset
System Reset
PCI Power Management Initiated Resets
Processor Initiated Resets
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