IBM PowerPC 604 User Manual page 65

The common pipeline stages are as follows:
• Instruction fetch (IF)-During the IF stage, the fetch unit loads the decode queue
(DEQ) with instructions from the instruction cache and determines from what
address the next instruction should be fetched.
• Instruction decode (ID)-During the ID stage, all time-critical decoding is
performed on instructions in the dispatch queue (DISQ). The remaining decode
operations are performed during the instruction dispatch stage.
• Instruction dispatch (DS)-During the dispatch stage, the decoding that is not
time-critical is performed on the instructions provided by the previous ID stage.
Logic associated with this stage determines when an instruction can be dispatched
to the appropriate execution unit. At the end of the DS stage, instructions and their
operands are latched into the execution input latches or into the unit's reservation
station. Logic in this stage allocates resources such as the rename registers and
reorder buffer entries.
• Execute (E)-While
the
execution stage is viewed as a common stage in the 604
instruction pipeline, the instruction flow is split among the six execution units, some
of which consist of multiple pipelines. An instruction may enter the execute stage
from either the dispatch stage or the execution unit's dedicated reservation station.
At the end of the execute stage, the execution unit writes the results into the
appropriate rename buffer entry and notifies the completion stage that the instruction
has finished execution.
The execution unit reports any internal exceptions to the completion stage and
continues execution, regardless of the exception. Under some circumstances, results
can be written directly to the target registers, bypassing the rename buffers.
• Complete (C)-The completion stage ensures that the correct machine state is
maintained by monitoring instructions in the completion buffer and the status of
instruction in the execute stage.
When instructions complete, they are removed from the reorder buffer (ROB).
Results may be written back from the rename buffers to the register as early as the
complete stage. If the completion logic detects an instruction containing exception
status or if a branch has been mispredicted, all subsequent instructions are cancelled,
any results in rename buffers are discarded, and instructions are fetched from the
correct instruction stream.
The CR, CTR, and LR are also updated during the complete stage.
• Writeback (W)-The writeback stage is used to write back any information from the
rename buffers that was not written back during the complete stage.
All instructions are fully pipelined except for divide operations and some integer multiply
operations. The integer multiplier is a three-stage pipeline. Integer divide instructions
iterate in stage two of the multiplier. SPR operations can execute in the MCIU in parallel
with multiply and divide operations.
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PowerPC 604 RISC Microprocessor User's Manual