Clock-Capable Inputs; Single Clock Driving A Single Cmt; Single Clock Driving Multiple Cmts - Xilinx 7 Series User Manual

For stacked silicon interconnect (SSI) device limitations with respect to clocking resource
selection, see

Clock-Capable Inputs

External user clocks must be brought into the FPGA on differential clock pin pairs called
Clock-capable inputs. Clock-capable inputs provide dedicated, high-speed access to the
internal global and regional clock resources. Clock-capable inputs use dedicated routing
and must be used for clock inputs to guarantee timing of various clocking features.
General-purpose I/O with local interconnects should not be used for clock signals.
Each I/O bank is located in a single clock region and includes 50 I/O pins. Of the 50 I/O
pins in each I/O bank in every I/O column, there are four clock-capable input pin pairs (a
total of 8 pins). Each clock-capable input:
•
•
•
Single-ended clock inputs must be assigned to the P (master) side of the clock-capable
input pin pair.
If a single-ended clock is connected to the P-side of a differential clock pin pair, the N-side
cannot be used as another single-ended clock pin—it can only be used as a user I/O. For
pin naming conventions, refer to UG475, 7 Series FPGA Packaging and Pinout Specification.
Clock-capable inputs are organized as 2 MRCC and 2 SRCC pairs in each I/O bank. SRCCs
access a single clock region and the global clock tree, and up to three CMTs. SRCCs can
drive:
•
•
•
MRCCs can access multiple clock regions and the global clock tree. MRCCs function the
same as SRCCs and can additionally drive multi-clock region buffers (BUFMR) to access
up to three clock regions.
Clock-capable inputs can be used as regular I/O if not used as clocks. When used as
regular I/O, clock-capable input pins can be configured as any single-ended or differential
I/O standard.
Clock-capable inputs can connect to the CMT in the same clock region, and the CMT in the
clock regions above and below with some restrictions.

Single Clock Driving a Single CMT

When a clock input drives a single CMT, the clock-capable input and CMT (MMCM/PLL)
must be in the same clock region.

Single Clock Driving Multiple CMTs

A single clock input can drive up to three CMTs. In this case, an MMCM/PLL must be
placed in the same clock region as the clock-capable input. The other CMTs must be placed
in adjacent clock regions above and below.
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Stacked Silicon Interconnect
Can be connected to a differential or single-ended clock on the PCB
Can be configured for any I/O standard, including differential I/O standards
Has a P-side (master), and an N-side (slave)
Regional clocks lines (BUFR, BUFH, BUFIO) within the same clock region
CMTs in the same clock region and adjacent clock regions.
Global clocks lines (BUFG) in the same top/bottom half of the device. Refer to 7 Series
FPGA Packaging and Pinout Specification for BUFG and I/O bank alignments.
www.xilinx.com
Clock-Capable Inputs
Clocking.
29