Xilinx 7 Series User Manual page 22

Chapter 1: Clocking Overview
Table 1-1: Summary of Clock Connectivity
Clocking Function or Pin
Multi-region Clock Capable
I/O (MRCC)
There are two pin/pairs in
each bank.
Single-region Clock Capable
I/O (SRCC)
There are two pin/pairs in
each bank.
BUFIO
www.BDTIC.com/XILINX
22
Directly Driven By
External Clock
External Clock
Within the same clock region,
BUFIOs are driven by:
• MRCCs (dedicated 1:1)
• SRCCs (dedicated 1:1)
• MMCM.CLKOUT0–
MMCM.CLKOUT3
• CLKFBOUT
• BUFMRs in the same clock region
and clock regions below and
above
www.xilinx.com
Used to Directly Drive
MRCCs that are located in the same clock region
and on the same left/right side of the device
drive:
• Four BUFIOs
• Four BUFRs
• Two BUFMRs
• One CMT (one MMCM and one PLL)
• CMTs above and below (using limited CMT
backbone resources).
MRCCs within the same half top/bottom drive:
• 16 BUFGs
MRCCs within the same horizontally adjacent
clock regions drive:
• BUFHs
SRCCs that are located in the same clock region
and on the same left/right side of the device
drive:
• Four BUFIOs
• Four BUFRs
• One CMT (one MMCM and one PLL)
• CMTs above and below (using limited CMT
backbone resources).
SRCCs within the same half top/bottom drive:
• 16 BUFGs
SRCCs within the same horizontally adjacent
clock region drive:
• BUFHs
When used within the same clock region, BUFIOs
drive:
• ILOGIC.clk
• ILOGIC.clkb
• OLOGIC.clk
• OLOGIC.clkb
• OLOGIC.oclk
• OLOGIC.oclkb
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012