Xilinx 7 Series User Manual page 24

Chapter 1: Clocking Overview
Table 1-1: Summary of Clock Connectivity (Cont'd)
Clocking Function or Pin
GT Transceiver Clocks:
RXOUTCLK
TXOUTCLK
MGTREFCLK0/1P
MGT positive differential
reference clock pins
MGTREFCLK0/1N
MGT negative differential
reference clock pins
CMT
IDELAYCNTRL.CLK
CCLK pin
EMCCLK pin
TCK pin
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Directly Driven By
N/A
External GT reference clock
• BUFG
• SRCC (same and adjacent clock
regions)
• MRCC (same and adjacent clock
regions)
• GTs in the same clock region
• A BUFR within the same clock
region, and the clock region above
or below using a BUFMR
• MMCM/PLL.CLKOUT0-3
• MRCC/SRCC
• BUFG
• BUFH
Configuration logic
N/A
N/A
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Used to Directly Drive
• BUFG within the same half top/bottom
When used within the same clock region, GTs can
drive:
• CMT
• BUFMR
• BUFH and BUFH in the horizontally adjacent
clock region
GT reference clock
• Any BUFG in same top/bottom half
When used within the same clock region, CMTs
can drive:
• BUFIO (MMCM)
• BUFR (MMCM)
• BUFH and BUFH in the horizontally adjacent
clock region
• MMCM/PLL (with phase offset if not
adjacent)
N/A
Configuration logic
Configuration logic
JTAG configuration logic and Boundary Scan
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012