Xilinx 7 Series User Manual page 77

match the forward clock buffer type with the exception of BUFR. BUFR can not be
compensated for.
CLKFBOUT – Dedicated MMCM and PLL Feedback Output
For possible configuration see
logic similar to the CLK0 of the DCM in Virtex-5 FPGAs.
CLKFBOUTB – Inverted CLKFBOUT
This signal should not be used for feedback. It provides an additional, inverted
CLKFBOUT output clock. CLKFBOUTB can drive logic similar to the CLK180 clock of the
DCM in Virtex-5 FPGAs. Not available in the PLL.
CLKINSEL – Clock Input Select
The CLKINSEL signal controls the state of the clock input MUXes, High = CLKIN1,
Low = CLKIN2 (see
during clock switchover.
RST – Asynchronous Reset Signal
The RST signal is an asynchronous reset for the MMCM/PLL. The MMCM/PLL will be
synchronously re-enabled when this signal is deasserted.
PWRDWN – Power Down
Powers down instantiated but currently unused MMCMs/PLLs. This mode can be used to
save power for temporarily inactive portions of the design and/or MMCMs/PLLs that are
not active in certain system configurations. No MMCM/PLL power is consumed in this
mode.
DADDR[6:0] – Dynamic Reconfiguration Address
The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration
address for the dynamic reconfiguration. The address value on this bus specifies the 16
configuration bits that are written or read with the next DCLK cycle. When not used, all
bits must be assigned zeros.
DI[15:0] – Dynamic Reconfiguration Data Input
The dynamic reconfiguration data input (DI) bus provides reconfiguration data. The value
of this bus is written to the configuration cells. The data is presented in the cycle that DEN
and DWE are active. The data is captured in a shadow register and written at a later time.
DRDY indicates when the DRP port is ready to accept another write. When not used, all
bits must be set to zero.
DWE – Dynamic Reconfiguration Write Enable
The dynamic reconfiguration write enable (DWE) input pin provides the write/read
enable control signal to write the DI data into or read the DO data from the DADDR
address. When not used, it must be tied Low.
DEN – Dynamic Reconfiguration Enable Strobe
The dynamic reconfiguration enable strobe (DEN) provides the enable control signal to
access the dynamic reconfiguration feature and enables all DRP port operations. When the
dynamic reconfiguration feature is not used, DEN must be tied Low.
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
MMCM and PLL Use
Reference Clock Switching). The MMCM/PLL must be held in RESET
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General Usage Description
Models. CLKFBOUT can also drive
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