Xilinx 7 Series User Manual page 108

Appendix B: Clocking Resources and Connectivity Variations per Clock Region
X-Ref Target - Figure B-1
Clock
Fabric - Multiple Columns of CLB/Block RAM/DSP
Backbone
CLB
25
CLBs
CLB
CLB
CLB
CLB
CLB
CE
Left Side
Clock
Connections
BUFH
or
BUFG
CLB
CE
CLB
CLB
CLB
CLB
25
CLBs
CLB
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108
5x36K 10x
Block RAMs/ DSP48
FIFOs Slices PLL
CLKA CLK
CLKB
Horizontal
Clocking
Row
5x36K 10x MMCM
DSP48
Block RAMs/
Slices
FIFOs
Figure B-1: Clock Region in Virtex-7 FPGAs (Right Side)
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Fabric - Multiple Columns of CLB/Block RAM/DSP
Block RAMs/
I/O Bank
SelectIO Logic CLB
SelectIO Logic
25
SelectIO Logic
CLBs
25
CLB
SelectIO
Logic Resources
CLB
BUFIO
CLB
BUFR
SelectIO Logic
CLB
BUFIO/BUFR
CLB
Any I/O Clock CC
BUFMR
Any I/O Clock CC
CLB
BUFIO/BUFR
SelectIO Logic CLB
BUFR
CLB
BUFIO
CLB
25
SelectIO
CLB
Logic Resources
25
SelectIO Logic
CLBs
SelectIO Logic
SelectIO Logic
CLB
Block RAMs/
7 Series FPGAs Clocking Resources User Guide
5x36K 10x
DSP48
GT Quad
FIFOs Slices
CLKA CLK
GTX/GTH
CLKB
RX/TXUSRCLKs
RX/TXOUTCLKs
IBUFDS O/ODIV2
GTX/GTH
RX/TXUSRCLKs
RX/TXOUTCLKs
IBUFDS O/ODIV2
HROW
GTX/GTH
RX/TXUSRCLKs
RX/TXOUTCLKs
IBUFDS O/ODIV2
GTX/GTH
RX/TXUSRCLKs
RX/TXOUTCLKs
IBUFDS O/ODIV2
5x36K 10x
DSP48
Slices
FIFOs
UG472_aB_01_020812
UG472 (v1.5) July 13, 2012