Regional Clocking Resources; Clock-Capable I/O; I/O Clock Buffer-Bufio - Xilinx 7 Series User Manual

Regional Clocking Resources

Regional clock networks are clock networks independent of the global clock network.
Unlike global clocks, the span of a regional clock signal (BUFR) is limited to one clock
region, one I/O clock signal drives a single bank. These networks are especially useful for
source-synchronous interface designs. The I/O banks in 7 series devices are the same size
as a clock region.
To understand how regional clocking works, it is important to understand the signal path
of a regional clock signal. The regional clocking resources and network in 7 series devices
consist of the following paths and components:
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Clock-Capable I/O

Each clock region has four clock-capable I/O pin pairs per I/O bank in every I/O column.
Clock-capable I/O pairs are specialized I/O pairs in select locations with special hardware
connections to nearby regional clocking resources and other clocking resources.
Additionally, clock capable I/O pairs can be used as regular I/O pairs. There are four
dedicated clock-capable I/O sites in every bank. When used as clock inputs, clock-capable
pins can drive BUFIO, BUFMR, and BUFR. Each I/O column supports regional clock
buffers (BUFR). There are two I/O columns in each device.
When used as single-ended clock pins, then as described in
of the pin pair must be used because a direct connection only exists on this pin.
A CCIO can drive any BUFR in the region, but only dedicated CCs can drive specific
BUFIOs and MRCCs can drive BUFMRs in a 1:1 relationship. This means that a CCIO has
only a single connection to a specific BUFIO or BUFMR.
I/O Clock Buffer—BUFIO
The I/O clock buffer (BUFIO) is a clock buffer available in 7 series devices. The BUFIO
drives a dedicated clock net within the I/O bank, independent of the global clocking
resources. Thus, BUFIOs are ideally suited for source-synchronous data capture
(forwarded/receiver clock distribution). BUFIOs are driven by clock-capable I/Os located
in the same bank, by the high-performance clocking (HPC) from the MMCM, or by the
BUFMRs in the same and adjacent regions. In a clock region, there are four BUFIOs per
bank. Each BUFIO can drive a single I/O clock network in the same region/bank. BUFIOs
cannot drive logic resources (CLB, block RAM, DSP, etc.) because the I/O clock network
only reaches the I/O column in the same bank/clock region. For multi-region bank
support, see
BUFIOs are driven by:
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Clock-Capable I/O
I/O Clock Buffer—BUFIO
Regional Clock Buffer—BUFR
Regional Clock Nets
Multi-Region Clock Buffer—BUFMR/BUFMRCE
Horizontal Clock Buffer—BUFH, BUFHCE
High-Performance Clocks
Multi-Region Clock
SRCCs and MRCCs in the same clock region
MRCCs in an adjacent clock region using BUFMRs
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Regional Clocking Resources
Buffer—BUFMR/BUFMRCE.
Global Clock Buffers the P-side
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