Xilinx 7 Series User Manual page 32

Chapter 2: Clock Routing Resources
Table 2-1: Clock-Capable Input Placement Rules (Cont'd)
Clock Inputs To
Only high-performance SelectIO
interfaces in up to two adjacent
(6)
clock regions
Notes:
1. Refer to Clocking Differences in 7 Series FPGAs, page
UG475, 7 Series FPGA Packaging and Pinout Specification, for CMT, BUFG, and I/O bank alignments.
2. Ensure that the clock-capable input pinout does not require more resources than available, i.e., more than the 16 BUFGs per "half"
of the device, one CMT per clock region, four BUFRs per clock region, etc. If more clocking resources are needed than are available,
the clock-capable inputs should be reassigned so that they can reach clocking resources in other clock regions.
3. If defining clock or high-speed bus interface pinouts for SSI devices, refer to the "Large FPGA Design Methodology Guide."
4. BUFH and BUFG use the same horizontal clock line resources within the clock regions. Each BUFG or BUFH uses one of the 12
horizontal clock lines in a clock region.
5. CLOCK_DEDICATED_ROUTE = BACKBONE is required when clock-capable inputs drive CMTs in other clock regions in the same
column but not in the same clock region.
6. When driving clocks into adjacent clock regions using the BUFMR or CMT, reduced clock resources can impact the adjacent clock
regions. For example, using a BUFMR to drive a BUFR in an adjacent clock region prohibits one of the clock-capable input pairs in
the adjacent clock region from driving the regional clock tree in its own clock region. A BUFH or BUFG can still be used to drive the
global clock lines in that adjacent clock region.
When migrating between devices in the same package, the top/bottom center line that
organizes BUFGs into 16 top and 16 bottom resources can appear to have shifted with
respect to the other columns. Specifically, the I/O banks change alignment to the top/
bottom BUFGs. This results in a different alignment of the CC input pins accessing the
BUFGs.
devices. In this case, the center line is lower (with respect to the I/O columns) when
moving from a large to a small device in the same package, or higher when moving from a
small to a large device. If the clock-capable input pins are LOCed, the design can be
unroutable.
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32
Resource Utilization and Placement Rules
Clock-capable input > BUFMR >BUFIOs > I/O clock tree
• Sequential I/Os and BUFIOs must be placed in the same
clock region as the clock-capable input, or in immediately
adjacent clock regions above or below.
• The BUFMR must be used to access BUFIOs and I/O clocks
in the same clock region and adjacent clock regions.
• A specific clock-capable pin pair connects to a specific BUFR
and BUFIO. Therefore it is not recommended to manually
LOC the BUFR/BUFIO.
• There are four clock-capable inputs, four BUFIOs, and two
BUFMRs per clock region.
25, for details on devices that have exceptions to these placement rules and
Figure 2-1 shows a center alignment example using the XC7K325T and XC7K160T
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(1) (2) (3)
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Valid
Clock-Capable
Input Pin
MRCC only