Xilinx 7 Series User Manual page 28

Chapter 2: Clock Routing Resources
BUFGCTRL (most often used as a BUFG) is the most commonly used clock routing
resource. These truly global clocks can connect to every clocking point on the device.
However, in some cases it is more advantageous to use alternate clocking buffers for either
performance, functional, or clocking resource availability reasons. BUFGs are best
deployed when:
•
•
•
•
•
The main purpose of the BUFR and BUFIO combination is to support source-synchronous
interfaces. When an interface is placed into a single region, the BUFIO clocks the
high-speed side of the SelectIOs and the BUFR clocks the deserialized/serialized side at a
lower speed into the FPGA logic providing the clock domain transfer function. For
interfaces that require more logic and/or I/Os than are available in a single clock region/
bank, the BUFMR (BUFMRCE) is used to expand clock domain transfer functionality into
the clock regions above and below. Certain types of applications that require a divided
clock not related to the source-synchronous I/O use case can use a BUFR as a simple clock
divider when an MMCM/PLL cannot be used or is not available for the frequency divide
function. In this case, particular attention must be paid to the timing and skew because this
is not the primary purpose of the BUFR. For more information on clocking SelectIO
resources, consult UG471, 7 Series FPGAs SelectIO Resources User Guide.
The horizontal clock buffer BUFH (BUFHCE) is strictly a regional resource and cannot
span clock regions above or below. Unlike BUFR, BUFH does not have the ability to divide
the clock.
•
•
•
•
•
•
•
www.BDTIC.com/XILINX
28
Designs or portions of a design have global reach across large areas of the device and
localization of functions is not possible.
Hardware functional blocks such as block RAM, DSP, or integrated IP that spans
many clock regions, are cascaded, or need connections to CLBs that are not nearby.
By switching clocks synchronous (glitch free) or asynchronous, applications are able
to switch away from a stopped clock or select a clock with a different frequency (e.g.,
power reduction).
The clock enable (CE) functionality can be used to reduce power during
non-operating periods. However, in most cases, the CE capability should not be used
to simulate a true CE logic function at the clocking elements due to timing (CE delay)
limitations.
The CE function can be used to synchronize initialized clocking elements after device
startup.
BUFHs are similar to a global clocking resource only on a regional basis spanning two
horizontal regions.
BUFHs have the ability to serve as a feedback to the MMCM/PLL and the clock
insertion delay can be compensated for.
BUFHs are the preferred clocking resource when an interface or cloud of logic can be
localized to one clock region or two horizontally adjacent clock regions.
The BUFH also has a clock enable pin (BUFHCE) that can be used to reduce dynamic
power consumption when either the logic or an interface and its associated logic are
not active.
The clock enable feature can provide a gated clock on a clock cycle-to-cycle basis.
Similar to the global clock tree, the BUFH can also connect to non-clocking resources
in the CLB (enable/reset) but with better skew characteristics.
BUFH can also be used for the synchronous startup of clocking elements in a clock
region.
www.xilinx.com 7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012