Xilinx 7 Series User Manual page 43

X-Ref Target - Figure 2-12
In
•
•
•
•
•
•
Table 2-5: BUFGMUX Attributes
BUFGMUX_CTRL
The BUFGMUX_CTRL replaces the BUFGMUX_VIRTEX4 legacy primitive.
BUFGMUX_CTRL is a clock buffer with two clock inputs, one clock output, and a select
line. This primitive is based on BUFGCTRL with some pins connected to logic High or
Low.
X-Ref Target - Figure 2-13
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
S
I0
I1
O
Figure 2-12: BUFGMUX_1 Timing Diagram
Figure 2-12:
The current clock is I0.
S is activated High.
If I0 is currently Low, the multiplexer waits for I0 to be asserted High.
Once I0 is High, the multiplexer output stays High until I1 transitions Low to High.
When I1 transitions from Low to High, the output switches to I1.
If Setup/Hold are met, no glitches or short pulses can appear on the output.
Attribute Name
CLK_SEL_TYPE Specifies synchronous or asynchronous clock
switching.
Figure 2-13 illustrates the relationship of BUFGMUX_CTRL and BUFGCTRL.
BUFGMUX_CTRL
I1
I0
S
Figure 2-13: BUFGMUX_CTRL as BUFGCTRL
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T
BCCCK_CE
T
BCCKO_O
ug472_c1_12_061310
Description
IGNORE1
GND
CE1
V
DD
S S1
I1
O
I0
S0
CE0
V
DD
IGNORE0
GND
Global Clocking Resources
Possible Values
SYNC (default),
ASYNC
O
ug472_c1_13_061310
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