Xilinx 7 Series User Manual page 84

Chapter 3: Clock Management Tile
Table 3-8: PLL Attributes (Cont'd)
Attribute
CLKFBOUT_MULT
DIVCLK_DIVIDE
CLKFBOUT_PHASE
REF_JITTER1
REF_JITTER2
CLKIN1_PERIOD
CLKIN2_PERIOD
STARTUP_WAIT Boolean FALSE, TRUE
Notes:
1. The COMPENSATION attribute values are documented for informational purpose only. The ISE software tools automatically select
the appropriate compensation based on circuit topology. Do not manually select a compensation value, leave the attribute at the
default value.
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84
Type Allowed Values
Integer 1 to 64
Integer 1 to 56
Real 0.0 to 360.0
Real 0.000 to 0.999
Real 0.938 to 52.631
Real 0.938 to 52.631
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Default Description
1 Specifies the amount to multiply
all CLKOUT clock outputs if a
different frequency is desired. This
number, in combination with the
associated CLKOUT#_DIVIDE
value and DIVCLK_DIVIDE
value, will determine the output
frequency.
1 Specifies the division ratio for all
output clocks with respect to the
input clock.
0.0 Specifies the phase offset in
degrees of the clock feedback
output. Shifting the feedback clock
results in a negative phase shift of
all output clocks to the PLL.
0.010 Allows specification of the
expected jitter on the reference
clock in order to better optimize
PLL performance. A bandwidth
setting of OPTIMIZED will
attempt to choose the best
parameter for input clocking
when unknown. If known, then
the value provided should be
specified in terms of the unit
interval (UI) (the maximum peak
to peak value) of the expected
jitter on the input clock.
0.000 Specifies the input period in ns to
the PLL CLKIN1 input. Resolution
is down to the ps. This information
is mandatory and must be
supplied.
0.000 Specifies the input period in ns to
the PLL CLKIN2 input. Resolution
is down to the ps. This information
is mandatory and must be
supplied.
FALSE Wait during the configuration
startup cycle for the PLL to lock.
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012